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In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
This paper presents an optimized architecture of shared memory controller in packet processing multi-processor system on chip (MPSoC). The rotation priority algorithm in arbitration mechanism is ameliorated so that fairness of the memory access response and continuity of read/write commands are guaranteed. A `ping-pong' structure is adopted in SRAM interface logic which optimizes the memory data throughput...
In a memory structure shared by multiple processors based on Multiprocessor Systems on Chip (MPSoC), the efficiency of memory bus access becomes the bottleneck of the overall system efficiency. This paper presents a low-latency SDARM controller structure integrated in MPSoC, which controls the off-chip SDRAM memory. Consecutive same row optimization and odd-even bank optimization are used to eliminate...
An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed...
In UHF RFID tag IC, multiple charge-pump stages are needed to form a rectifier for achieving a sufficiently high output voltage to supply the other circuit blocks. To save chip area and achieve a high output voltage simultaneously, the number of charge-pump stages should be optimized in accordance with the amplitude of the RF input signal. In this paper, an analysis on the relation between the output...
A low-power single-channel sub-sampling 3-bit 4GS/s flash ADC in 0.13-μm CMOS is presented. Resistive averaging network and multi-stage interpolation technique are introduced for offset cancellation and power reduction, respectively. The comparator uses CML (current mode logic) blocks and pipelined structure to further enhance the speed of ADC. The simulation results reveal that the ENOB is 2.9 bit...
In this paper, an advanced charge pump optimization methodology based on DOE technique is proposed. Compared with other optimization methods, this methodology constructs accurate mathematical models between the outputs and the input parameters with a few simulations through response surface technique and regression analysis. Moreover, owing to the simplification of the number of main charge pump input...
Hummingbird algorithm is a newly proposed lightweight cryptographic algorithm targeted for low-cost RFID tag. In this paper, we present a hardware implementation of this algorithm using SMIC0.13 μm CMOS process. Methods are used to reduce the unnecessary clock toggling and data toggling to reduce dynamic power. Simulation results show that the total area of our design is 14,735 μm2. It requires 16...
In this paper, we use design planning method to partition a flat design based on SAED 90 nm process technology into blocks and created interface logic models (ILMs) for each blocks. Using the hierarchical design including ILM, the runtime of the place optimization stage, clock optimization stage and route optimization stage is reduced to 28.8%, 27.7% and 43% relatively, meanwhile the boundary timing...
Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture...
With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller...
Power Gating(PG) is very effective to reduce the leakage power. Recently proposed Zigzag power gating(ZPG) technique has the visible advantage on short wake-up time. However, additional PG transistors consume intolerable area overhead. Basing on the BPTM-65nm model, we propose a new optimization methodology of the selective ZPG technique for the wide-used dual-threshold voltage CMOS circuit design...
La2O3 insulators have been prepared by ALD using La(iPrCp)3 and H2O as the source materials. We identified two necessary conditions to achieve the self-limiting growth: temperatures lower than 200°C and extremely long purging after H2O pulses. La2O3 insulators annealed at 500°C showed good MOS properties with no hysteresis and small flat-band voltage shift. Comparisons to the have La2O3 films prepared...
Graphene, a two-dimensional carbon form with the highest intrinsic carrier mobility and many desirable physical properties at room temperature, is considered a promising material for ultrahigh speed and low power devices with the possibility of strong scaling potential due to the ultra-thin body. (Fig. 1) [1-3] Here IBM reports progress in graphene nanoelectronics, synthesizing wafer-scale monolayer-controlled...
A Magnesium Doped Layer (MDL) under the 2-DEG channel and a Drain Metal Extension (DME) are proposed to provide a new degree of freedom in the optimization between breakdown voltage (BV) and specific-on-resistance (Ron-sp) in AlGaN/GaN HEMTs. The surface electric field of the proposed structure is distributed more evenly when compare to the MDL-only structure with the same dimensions. A breakdown...
The optimization of the electrode structure plays an important role in the improvement of the charge collection efficiency of diamond film radiation detector. In this paper the finite element (FE) method is utilized to design and optimize the electrode geometry. For 1×1 cm2 diamond film model, the detector provided the best charge collection efficiency and energy resolution, when the ratio of the...
A new extraction method for InGaP/GaAs HBTs based on direct optimization is proposed. Through modification of conventional GP formulation, the variations of transport saturation current and ideal forward transit time versus biases are incorporated into the compact model. Rather than intense and complicated iterative optimization, this new parameter extraction methodology realized the united optimization...
Today the research on design for testability is becoming the research priority in the filed of SoC. However, the traditional research is limited in top level of SoC and it ignores the inference resulting from the scheduling strategy in IP-core level. In addition, the work on stage of SoC overly focuses on researching the minimum testing time of different WSC. It ignores the relationship between the...
The paper described a novel improved version based on Integrated Operand Scanning (FIOS) algorithm, which would be beneficial to hardware implement in parallel. And a new fault resistant scheme for our proposed algorithm was also shown in this paper via comparing the intermediate variables with those recomputed during idle time. The total cycle maybe reduce by about 40% of original one and the capability...
In this paper, we introduce a multiple threads model for video decoding optimization which automatically adjusts the thread priority among decoding threads, and verify the test results on Marvell ARMADA 610 processor. The test results show that the performance of video decoding is improved about 250% comparing with the single thread model, and about 3.5% faster comparing with traditional multiple...
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