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Analog-to-digital conversion plays an essential role in all kinds of electronics systems, including signal processing, communications and storage. In particular, interpolated flash ADC has been widely used in high-speed systems requiring very high sampling speed. Obviously, practical ADC design is very challenging, which has been dominated by experiences and trial-and-error skills. This is true to...
The single analog filter (SAF) hybrid filter bank (HFB) ADC is presented in this paper. Base on SAF architecture, a calibration model is derived to integrate the analog filter's realization errors and channel mismatches errors. A two-channel SAF HFB ADC with 12-bit resolution and 200MHz sampling rate is implemented. The experimental results show that the average spurious-free dynamic range (SFDR)...
A simple digital background-calibration technique is proposed for a pipelined analog-to-digital converter (ADC). Both gain error and DAC error are measured and calibrated by injecting two uncorrelated pseudo-random sequences into the MDAC. With this method, not only small capacitors might be used, leading to small chip size, but also the traditional current starving high gain op-amps of pipelined...
With the amount of calculation for wireless and multi-media applications increasing, the Multi-Processor System-on-a-Chip (MPSoC) based on Network-on-Chip (NoC) is used to process massive data in a distributed fashion. Compared with heterogeneous architecture for general embedded low power DSP, homogeneous NoC architecture is much more flexible for dynamical task assignment. In this paper, a new NoC...
In this paper we present a technique that permits the correction of errors caused by the timing jitter associated with sampling clocks cadencing analog-to-digital converters (ADCs). The correction system is digital, completely independent of the front-end ADC and corrects the data out of the converter on a sample-to-sample basis. Relative to the ADC under consideration, the proposed technique enables...
In a memory structure shared by multiple processors based on Multiprocessor Systems on Chip (MPSoC), the efficiency of memory bus access becomes the bottleneck of the overall system efficiency. This paper presents a low-latency SDARM controller structure integrated in MPSoC, which controls the off-chip SDRAM memory. Consecutive same row optimization and odd-even bank optimization are used to eliminate...
This paper presents a novel first-order temperature compensated current reference. The measured temperature coefficient of this current reference is less than 290 ppm/°C over the temperature range from -20°C to 110°C. What's more, it is compatible with standard CMOS technology, which makes its application more flexible.
This paper described a digitally controlled Buck converter. In this converter, the compensator implements the classic linear PID control law by the fixed-point algorithm. A proposed verification method is performed in Simulink environment. The structure of low area and power cost Ring ADC and high resolution DPWM is also introduced, respectively. The consistent mathematic and Spice simulation result...
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate...
A wide tuning range LC VCO with auto amplitude control is designed in 0.13-μm CMOS. Phase noise optimized design for the wide tuning range VCO is discussed and a PVT insensitive digitally reconfigurable auto amplitude calibration (AAC) circuit is used to stabilize the phase noise in the whole wide band. The proposed AAC circuit with a code estimated FSM provides faster operation to get the optimum...
This paper presents a 1.2V CMOS RSSI based on successive detection structure. An equation estimating the maximum nonlinear error is derived and the simulation results show it is more accurate than the former one proposed by P. C. Huang. The RSSI achieves a wide bandwidth from 1MHz to 500MHz. The linear dynamic range is at least 80dB. The nonlinear error based on single frequency curve fitting is within...
The paper present an ultra-low power NEO using full-CMOS technology based on sub-threshold analog design. The ultra-low power NEO system includes a differentiator with a differential structure and a multiplier based on the dynamic translinear principle. The circuit has been designed in 0.35μm CMOS technology and with total current consumption of about 825 nA. As is demonstrated by the simulation results,...
This paper reports a new recursive algorithm for efficient estimation of the noise content in time-domain noise analysis of non-linear dynamic integrated circuits with arbitrary excitations. Statistical simulation of specific circuit fabricated in 65 nm CMOS process shows that the proposed algorithm offers accurate and efficient solution.
A systematic methodology for opamp synthesis is presented. Based on this methodology, an automatic computer-aided design (CAD) tool called OTACAD is developed. OTACAD directly uses HSPICE as the simulator and a lookup table to model MOSFET in saturation region without complex equations. So it can design opamps in deep-sub-micron technologies and is suitable for various CMOS processes. Then, A sample...
Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail,...
Based on the exact solution of the Poisson's equation, a new two-dimensional (2-D) model for the silicon-on-insulator (SOI) fully-depleted four-gate transistor(G4-FET) is successfully developed. The model is verified by its good agreement with the numerical simulation of the device simulator. For the threshold voltage degradation, it is found that the lateral coupling effects between lateral gate...
Compact modeling of a Si nanowire MOSFET is discussed. Framework and detailed expression of the compact model for a ballistic Si nanowire MOSFET are provided. The device characteristics of a thin Si nanowire MOSFET is shown as a model calculation, and some characteristic features of the device are explained. Then a new scattering model for a quasi- ballistic Si nanowire MOSFET is introduced, and the...
Stack-transistor structure is often used in RF applications for higher power handling capability and/or isolation. LDMOSFET may provide similar advantages with smaller device area and lower series resistance. The purpose of this work is extracting the RF parameters of a LDMOSFET and design a RF switching circuit with these parameters. The design trade-off between LDMOS and CMOS technologies was discussed...
The thermal diffusion behavior of ion-implanted Arsenic (As) in SiGe alloy has been investigated and modeled. This paper introduces an empirical model consisting of physics-based and process parameters for evaluating the effective diffusivity of Arsenic through SiGe accurately. The process parameters that were found to dominate the enhancement in arsenic diffusion were the Germanium content, diffusion...
This work studies the electrical and testing reliability issues of CuxO based RRAM (Resistive Random Access Memory). Firstly, we study the most important electrical reliability issue-data retention capability, and propose a filament/charge trap combined model to clarify the retention failure mechanism. Secondly, we respectively study the reliability problems caused by the SET compliance current in...
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