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A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window...
A lateral power MOSFET with the extended trench gate is proposed in this letter. The polysilicon gate electrode is extended to the substrate, which improves the breakdown voltage (BV) and specific on-resistance (Ron). It indicates by simulation that the Ron of 1.86mΩ.cm2 with a BV of 174V in the proposed structure is nearly 53% less than the Ron of 3.96mΩ.cm2 with a BV of 126V in the typical structure.
A superjunction LDMOST with a floating oppositely doped buried layer in p-substrate is proposed. The buried layer provides another pn junction to sustain drain voltage, reduces the substrate-assisted-depletion effect and generates new electric field, which modulates the bulk electric field in off-state. Simulation results show that the proposed structure achieves significant breakdown voltage improvement...
In this study, we investigated the electrical characteristics of p-channel transistor by changing the process sequence of P+ Source/Drain Ion Implantation (IIP) N2 annealing process in NAND Flash memory. For the case of changing the process sequence of N2 annealing, off-current of p-channel transistor was dropped sharply, and increase of the on current compared to the off current is not worse than...
The high breakdown voltage AlGaN/GaN HEMTs with source-terminated field plate was firstly fabricated for high frequency and high power application, employing by CF4 plasma treatment for enhancement-mode (E-mode). The results showed that by adding the distance of gate to drain, LGD from 5 um to 15um, the breakdown voltage of the device was rapidly increased 350V, whose value is from 50V to 400V while...
High breakdown voltage GaN HEMTs was developed for power electronics application. The device with source connected field plate (FP) was fabricated, which demonstrated perfect hard breakdown characteristics. A high breakdown voltage of 740V was obtained in air ambient while gate-drain spacing Lgd and FP length LFP equaled to 20μm and 2μm respectively. Specific on-resistance of the device was 14mΩ.cm...
The first material of silicon dioxide (SiO2) had been proposed as a chemical transducer element of pH sensitive membrane around the early of 1970s. In 1981 Matsuo et al. proposed Ta2O5 as pH sensing membrane. Start from that moment, many materials have been wildly investigated, e.g. Al2O3, SnO2, WO3. The rare -earth oxide, Samarium oxide (Sm2O3), is an attractive material to substitute the previous...
Normalized Differential Conductance Spectroscopy (NDCS) has been used to investigate the tunneling properties of post soft breakdown SiO2. It is shown that the NDCS is capable of separating various components of tunneling current and determining its corresponding tunnel constants of post SBD SiO2. Therefore, the most important tunneling parameters: the effective mass of tunneling electron in SBD SiO...
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
This paper proposed an advanced logarithm cofactor difference operator (LogCDO) method to extract parameters of the MOS devices' post-breakdown current. The experimental results of the post breakdown current in MOS devices at different temperature are used to demonstrate the validity of the advanced LogCDO method. The post-breakdown current is equivalent to a dual diode circuit model, and then the...
High power microwave (HPW) can cause the semiconductor devices failure,thereby make the electronic system work anomaly. Bipolar transistors are the typical semiconductor devices. In this paper, the effect of HPM on the bipolar transistors is studied through the HPM injection experiment. The experiment results show that the HPM injected into the devices could cause the degradation, distortion and damage...
The dependence of the avalanche breakdown voltage on vertically linear doping gradient of the drift region based on Silicon-On-Insulator (SOI) lateral diffuse metal oxide semiconductor (LDMOS) is studied. Vertically linear doping profile (VD) of the LDMOS structure is exhibited to obviously improve safe of operation area (SOA) from the conventional uniform and variable linear doping structure. From...
A 2D analytical model of the bulk-silicon triple RESURF devices is proposed. Based on the 2D Poisson's solution, the new analytical expressions of the surface potential and electric field distributions are obtained. According to the model and the semiconductor device simulator Medici, the electric field reduction mechanism and breakdown characteristics in the device are discussed. Further, a RESURF...
A vertical pnp BJTs on thin SOI is designed and characterized by using the mixed numerical two-dimensional process and device simulator (Sentaurus). The DC, frequency, and breakdown characteristics of the vertical pnp on SOI are simulated and analyzed. The peak of β is 85 at Vbe=-0.7. The maximum of the cutoff frequency fτ for the pnp bipolar transistor on SOI attain 10.6 GHz, and the value of BVceo...
One way to increase the breakdown voltage in heterojunction field-effect-transistors (HFETs) on silicon substrate is to introduce a transition (buffer) layer made of a sandwich of thin AlN/AlGaN layers between the silicon substrate and the GaN well. The effect of this transition layer is to average out and, in this way, to reduce the local mechanical stress that appears between the silicon substrate...
A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (EI) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown...
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