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For transistor research and development, one of the important figures of merit is the carrier mobility. The measurement of mobility is cumbersome in large devices, and nearly impossible in nano scale devices. Very often, effective mobility (μeff) is extracted from the I-V curve instead. There are many pitfalls in equating μeff to mobility (μ), including charge-trapping and series resistance effects...
This paper introduces a number of current-mode input configurations for gigabit CMOS optical receivers, including common-gate, regulated-cascode (RGC), current-mirror, etc. Unlike conventional voltage-mode input configurations, the current-mode designs effectively isolate the large input parasitic capacitance from the determination of the bandwidth, hence achieving wide bandwidth for comparable transimpedance...
This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
The requirements of segmented current-steering DAC's MSB part for transistor matching are very high. In this paper, a diagonal layout is presented which can meet very well the requirements of 12-bit DAC monotonicity. The DAC was developed in TSMC 0.18um process technology. As a result of measurements, the static errors are: DNL=±0.15LSB, and INL=±0.2LSB.
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
This paper presents a novel first-order temperature compensated current reference. The measured temperature coefficient of this current reference is less than 290 ppm/°C over the temperature range from -20°C to 110°C. What's more, it is compatible with standard CMOS technology, which makes its application more flexible.
In this paper, a 4-channel photocurrent detector is described which is used in the field of photoelectric detection. Each channel of the detector consists of TIAs and voltage comparator, and current detection threshold can be set by external voltage. The TIA has measured 1.5mA input current overload capacity and 1.9 nArms equivalent input noise current level. The detector is processed in 2 um all-NPN...
Silicon nanowire transistor with side-gate and back-gate has been fabricated by electron beam lithography combined with dry oxidation on a doped silicon-on-insulator wafer. The effects of back-gate and side-gate on the properties of single electron transport were investigated by measuring the channel current as function of the applied gate voltages. The tunable single electron effect and Coulomb oscillations...
A new type of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with self-aligned metal electrodes (SAME) is systematically characterized. New device features different from conventional poly-Si TFTs are found, and are attributed to the presence of Schottky barriers at the channel ends.
A new structure of high-voltage junction FET was designed by using a 40 V LDMOS technology without additional mask in this process. This JFET also has the same breakdown capability as the LDMOSFET. The pinch-off voltage of the JFET was determined by layout, the n-well opening. The pinch-off voltage was almost unchanged with temperature variation. This JFET can be used in circuit applications with...
Chemical Vapor Deposition (CVD) of Ga on Si is performed in a commercial Si/SiGe epitaxial reactor at temperatures from 400 - 650 °C and conditions for which the Ga deposits selectivity on Si and the reactivity of the Ga with Si is so low that a thin-film deposition is achieved. Contact windows to c-Si are covered with a thin layer of Ga and contacted by sputtering Al/Si(1%). On the basis of an extensive...
In this paper, we use a novel way to research the piezoresistance coefficients of AlGaN/GaN HEFT affected by the changes of temperatures in the structure of micro-accelerometer. It is shown that saturation current of HEFT would decrease with the increasing temperature, which is about 0.028mA/°C. However, the device can work well at the temperature range of -50°C to 50°C, which indicates that it can...
Electrostatic discharge (ESD) protection becomes essential to advanced integrated circuits (IC). Very fast IEC-ESD failure and protection design are emerging challenges for contemporary ICs, particularly for consumer and portable electronics. This paper presents a new mixed-mode IEC-ESD simulation-design method, which involves process, device, circuit and system level simulation to accurately address...
The conventional threshold voltage shift measured by extrapolating transfer characteristics, ΔVth(ex), underestimates the NBTI-induced degradation of drain current, ΔId. Mobility degradation, Δμ, has been proposed as a potential contributor to ΔId. Evaluating Δμ, however, can be problematic and controversial. For test engineers, it is desirable to include all degradations in one parameter and we propose...
Space applications using advanced foundry processes require accurate assessment of the dependence of total-ionizing dose (TID) response on process variability and layout. A new test chip is described to enable large sample of device measurements under irradiation. The variability of TID-induced leakage current and transistor mismatch both increase after irradiation.
This work presents the mechanism of Stress induced leakage current (SILC) under NBT stress. Experiment results show that there are three kinds of oxide traps generated under NBT stress: hole traps with full recoverable characteristic, hydrogen related traps with irrecoverable characteristic and a kind of positive trap which can promote the hole tunneling after neutralization. The cause of SILC is...
The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow...
Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching...
A new procedure to determine source/drain series resistance and effective channel length has been developed for MOSFETs operated in linear region. The gate-bias dependence of source/drain resistance is considered by differential and integration processes. This new-developed procedure has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The parameters extracted with this...
In this paper we present the modeling of low frequency in 0.18um PDSOI technology. The two main noise sources, 1/f and excess noise due to shot noise have been discussed. It has been shown that accurate modeling of the body voltage, impact ionization, diode currents and 1/f noise characteristics is essential to incorporate the correct bias and frequency dependence of this excess noise component. Model...
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