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A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
A current buffer compensation Low Dropout (LDO) regulator for portable applications is present in this paper. The current buffer compensation scheme is a current feedback amplifier, which provides low output impendence in order to move the non-dominant pole due to the large gate capacitance of the pass transistor of the LDO regulator to high frequency. This LDO circuit had been designed and implemented...
A fourth-order switched-capacitor bandpass ΔΣ modulator is presented for digital IF receivers. The circuit operates at a sampling frequency of 100MHz. It is implemented in a 0.13-μm standard CMOS process. The measurement shows that signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) achieve 68dB and 75dB, respectively, over a bandwidth (BW) of 200kHz and power dissipation is 8.2mW at...
This paper presents a high gain and wide bandwidth fully differential operational amplifier (op amp) used in a sample and hold amplifier (SHA) circuit for a 12bit, 50Ms/s pipelined ADC. The gain-boosted technique is adopted to achieve a high gain without reduction of the output swing, while a new frequency compensation method is developed to compensate the bandwidth degradation caused by the gain-boosted...
A compact automatic gain control (AGC) loop for GNSS RF receiver is presented in this paper. The proposed AGC loop circuit achieves higher integration and lower power by eliminating the bulky off-chip capacitor and charge pump circuit, which are widely used in traditional AGC. The proposed AGC consists of a programmable gain amplifier (PGA), a 2-bit flash analog to digital converter (ADC), and a novel...
This paper presents a 10-bit 200MS/s CMOS current-steering digital-to-analog converter (DAC) with on-chip testbench. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. The measurement results show that the converter achieves a spurious-free dynamic range (SFDR) up to 78.7dBc. The full-scale output current is 20mA with 3V power supply for analog...
A 14-bit 100MS/s self-calibrated Digital-to-Analog converter (DAC) is presented. Analog background self-calibration technique with a randomized calibration-period is adopted to improve the dynamic performance. The DAC is fabricated in SMIC 0.13-μm CMOS process and occupies a 1.29mm2 die area. The measured DNL/INL is better than 3.1LSB/4.3LSB. The SFDR is 72.8dB at 1MHz signal and 100MHz sampling frequency...
This paper presents an improved area-efficient design method to construct interpolation filter of Sigma-Delta audio digital-to-analog converter (DAC). Several architectures and implementation techniques are adopted to reduce the complexity of the system. The Matlab simulation, FPGA verification and digital synthesis are performed to support the feasibility of the presented method. The cell area of...
Direct digital frequency synthesizer (DDFS) plays an important role in modern digital communications. This paper proposes a novel implementation of a 300MHz direct digital frequency based on modified CORDIC in 0.35μm CMOS technology. The CORDIC algorithm is a well-know iteration method for the efficient computation of fundamental functions, but each iterate selects the rotation direction by analyzing...
A CMOS capacitor-free low-dropout (LDO) voltage regulator with 0.65-1.8 V power supply is presented. Positive feedback is used to build the differential computation of the error amplifier and the positive feedback gain is less than unity to ensure the stability. The LDO is designed in TSMC 0.18 μm CMOS processes. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The simulation...
In this article, an optimized transient performance CCL-LDO is proposed, which adopts the controlling method of the charge pump phase-locked loop. With 1μF decoupling capacitor, the experimental results based on 0.13μm CMOS process show that the output voltage is 1.0V, and when the workload changes from 100μA to 100mA transiently, the stable dropout is 4.25mV, settling time is 8.2μs and undershoot...
In UHF RFID tag IC, multiple charge-pump stages are needed to form a rectifier for achieving a sufficiently high output voltage to supply the other circuit blocks. To save chip area and achieve a high output voltage simultaneously, the number of charge-pump stages should be optimized in accordance with the amplitude of the RF input signal. In this paper, an analysis on the relation between the output...
This paper described a digitally controlled Buck converter. In this converter, the compensator implements the classic linear PID control law by the fixed-point algorithm. A proposed verification method is performed in Simulink environment. The structure of low area and power cost Ring ADC and high resolution DPWM is also introduced, respectively. The consistent mathematic and Spice simulation result...
An analog baseband chain for WiMedia MB-OFDM UWB and China UWB standard is presented. The baseband chain consists of a fifth-order chebyshev type low pass filter with two switchable cut-off frequencies. A programmable gain amplifier based on enhanced source degeneration architecture is also included. The chip was fabricated in TSMC 0.13-μ RF CMOS process. Measurement results show that the analog baseband...
A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in...
In this paper, the detailed design procedure for two operational amplifiers (OP-Amp) used in charge pumps (CP) is presented. Such procedure, which is from system-level specifications to circuit-level requirements, provides a general methodology for OP-Amp design in CP. The design was simulated in a 0.18μm CMOS process and occupies a layout area of about 200μm×100μm. The simulation results show that...
A low-power, capacitor-free low-dropout regulator (LDO) with Pseudo-Input stage feedforward compensation (PISFFC) is proposed in this paper. This novel FFC technique, employing the method of capacitive-coupling to provide large dynamic current for driving power transistor, is highly integrated, widely applicable and can provide ultra-fast load transient response. Compared to conventional slew rate...
A 1.8 V-to-10 V high-voltage tolerant level shifter (HVT level shifter) is presented in this paper. This new topology of HVT level shifter makes all the transistors working in safe operating region, and consequently greatly enhances the circuit's reliability. It has been fabricated in 0.18 μm CMOS process, and successfully integrated in an embedded EEPROM memory with 10 V programming/erasing voltages...
A novel frequency hopping technique is proposed to increase the efficiency in a switched-capacitor LED driver, based on analyzing the dependence of power loss on switching frequency. LEDs' load current is featured uniquely by jumping periodically from a constant value (20mA) to zero for dimming function. Developed on an improved VCO, the hopping technique makes the switching frequency vary discretely...
A switch-mode Li-ion battery charger is proposed. It is suitable for input power supply of wall adaptor or USB port in modern portable apparatus. When it works under USB port supply, its input current is automatically limited at a presetting value. A power-path management is introduced in to realize charging and power supply simultaneously based on load priority. It also realizes smooth transition...
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