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In this paper, a novel low-power SRAM based on 4-transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation...
A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
Analog-to-digital conversion plays an essential role in all kinds of electronics systems, including signal processing, communications and storage. In particular, interpolated flash ADC has been widely used in high-speed systems requiring very high sampling speed. Obviously, practical ADC design is very challenging, which has been dominated by experiences and trial-and-error skills. This is true to...
Energy efficiency plays an important role in the design of high performance analog CMOS circuits. In medium- to high accuracy circuits, it is becoming increasingly difficult to maintain energy efficiency as CMOS technology is scaled to nanometer dimensions. This paper discusses some of the important challenges often faced by analog designers working with nanoscale CMOS technologies and reviews state-of-the-art...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
This paper reports a Digitally Controlled Oscillator (DCO) with 20kHz frequency resolution. This is the first DCO implementing capacitor delta tuning and Dynamic Element Matching (DEM) to suppress process variations and mismatches between small capacitor deltas. The DCO is fabricated in 0.13μm CMOS IBM technology. The proposed DEM technique reduced the process variations and mismatches from 95% to...
Stability is a critical design issue for radiation detection readout circuit when high counting rate together with low power property is simultaneously required. In this letter a novel method which increases the phase margin of the pulse shaper is presented. A readout circuit using this compensation technique has been implemented in 0.35 μ CMOS technology. Simulation and test results show that this...
This paper presents an active low-pass filter with its bandwidth ranging from 100Hz to 8kHz. The signals lower than 500Hz are filtered through the switched capacitor low-pass filter, while those higher than 500Hz are filtered through the continuous-time one. Problems such as charge injection and clock feedthrough in the switched-capacitor circuit are also analyzed and worked out in this design. We...
This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance...
This paper presents a wireless monitoring system. It consists of a novel capacitive angle sensor, a sensing-processing circuit and a low power remote control unit. The sensor is made up of integrated capacitance array which is covered with a seal box. Conducting liquid in the box connects certain capacitors with measuring circuits to acquire angle degree under gravity action. The sensor and the sensing-processing...
In the last years the MOS transistor technology has reach very high cut-off frequencies (near to 500 GHz), thanks to the continuous reduction of the channel length, but the short-channel-effects (SCE) strongly affects the MOSFET behavior below 60 nm. For such technology nodes the Multiple-Gate transistor (MuGFET) appears as a promising alternative to continue with the International Technology Roadmap...
An overview is given for the current state-of-the-art of tunable RF elements. For this purpose, tunable RF elements such as thin-film Barium Strontium Titanate (BST) varactors, Micro Electro Mechanical Systems (MEMS) based capacitive switch banks and varactors, as well as semiconductor based capacitive switch banks and varactors are reviewed. Their benefits and shortcomings are discussed and compared...
The design flow of a lumped Elements varactor-loaded Transmission-Line phase shifter (VLTL) is illustrated and a 60 GHz phase shifter of this kind is implemented in IBM 90nm CMOS process in this paper. The proposed VLTL is area-saving, occupying only 937um × 110um as it uses inductors instead of long transmission lines. This phase shifter is digitally controlled and need no extra DACs to realize phase...
In this paper, based on the interdigital capacitance, a kind of optimizing approach by tuning length of the interdigital lines respectively is presented. And the workload could be reduced greatly when this approach is applied to the left-handed transmission line(LH-TL) design. From the simulation results, it can be seen that the passband width of the LH-TL could be increased significantly. After that,...
With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller...
A high isolation and low insertion loss transmit/receive switch is presented. The T/R Switch is based on the TSMC 0.18 μm 1P6M RFCMOS process. Shunt inductor resonance and body-floating techniques are used to improve the isolation and power handling capability. The simulation exhibit the insertion loss is 612mdB, the isolation between transmitter and receiver is 44.3 dB, input 1-dB compression point...
Three-Dimensional (3D) integration will take the next stage VLSI technology instead of 2D technology. In 3D chip, the electrical performances are much better than in 2D chip, for its short length. In this paper, an accurate energy consumption model of 3D Through-Silicon-Via (TSV) is proposed for power estimation of 3D Network- on-Chip (NoC). The capacitance model of isolated TSV is analyzed in detail,...
The edge field enhanced deep depletion phenomenon in metal-oxide-semiconductor (MOS) structure was demonstrated. The analysis in inversion to deep depletion of ultra-thin SiO2 and HfO2 was conducted using critical field model. By examine the field ratio between edge and bulk, it is observed that the HfO2 has larger ratio than SiO2. It is supposed the edge field enhanced deep depletion phenomenon dominates...
Compact modeling of a Si nanowire MOSFET is discussed. Framework and detailed expression of the compact model for a ballistic Si nanowire MOSFET are provided. The device characteristics of a thin Si nanowire MOSFET is shown as a model calculation, and some characteristic features of the device are explained. Then a new scattering model for a quasi- ballistic Si nanowire MOSFET is introduced, and the...
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