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This paper introduces a voting scheme for safety-related analog input module to arbitrate between the results of redundant channels in fault-tolerant system. The design approach is a distributed system using a sophisticated form of duplication. For each running process, there is a backup process running on a different CPU. The voter is responsible for checkpointing its state to duplex CPUs. In order...
In order to resolve the poor suppression capability of noise and fitter interference existing in grating encoder high-rate subdivision and the poor accuracy of kam-to, counting circuit, we design a circuit based on FPGA to realize multiplier, kam and filter for the output of two-way orthogonal signal generated by Incremental Optical Encoder. The system is mainly divided into three modules such as...
An equivalent optimized sub-pipelined architecture is proposed to implement the AES, every round including encryption and decryption needs one clock cycle. The SubBytes/InvSubBytes operation using composite field arithmetic in GF(24) and BlockRAMs respectively. In addition, an efficient key expansion which supports the output of 128 bits key per cycle and allows key changes every cycle is also presented...
This paper introduce the arithmetic design of fuzzy control based on FPGA and the application of chemical manufacture process control. The method of its implementation and parameter selection are proposed. The experimental result shows that the temperature control performance of this regulatory system following the mode of fuzzy control is better than PID control, especially in the ways of working...
Speeding is recognized as a major contributing factor in traffic accidents on freeway. In order to reduce speed-related accidents, accurate real-time speed limit enforcement system is very critical to freeway. This paper presents an automatic speed limit enforcement system on freeway based on cameras and the Field Programmable Gate Array (FPGA) implementation to achieve this objective. Taking the...
This paper introduces a process to select different test circuit using FPGA controlled pull and disconnection of relay matrix, so that multi-port equipment testing could be achieved. This design, to some extent, has a simplified circuit complexity and an increased, comparing to the test equipment previously used.
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