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As CMOS scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full CMOS compatibility, such as Logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility...
This paper describes a low swing differential signaling scheme for on-chip global interconnects. A simple MOS current mode logic circuit is used to provide an attractive alternative to conventional full swing voltage signaling. The most traditional low swing drivers use additional reference voltages to limit the signal swing. By applying the proposed circuit, a low voltage swing of 110 mV can be obtained...
In this paper, we propose a novel on-chip global interconnect that would meet stringent challenges of core-to-core communications in data rate (up to 100 Gbps /link), latency and re-configurability for future chip-microprocessors (CMP) with efficient area and energy overheads. We discuss the limitations of traditional RC-limited interconnects and possible benefits of multi-band RF-interconnect (RF-I)...
The integration of today??s complex multi-power domain IOs, inherited from legacy ??Reuse IP?? sources, poses a big challenge to the full chip physical integration in terms of product cost and design cycle time for products such as Tolapai, the first IA based SoC with IA CPU core, South bridge (ICH), North bridge (MCH), acceleration hardware and networking interfaces. To meet these challenges, the...
In recent SOPC (System on Programmable Chip) design, a system becomes very complex and the cost of modifying the design during the development becomes very expensive. Based on the technology of the C to HDL (Hardware Description Language), we propose a framework to convert C++ class to hardware, which can be used to cope with the change of design requirement during the development period. Within this...
On-chip interconnects form the bottleneck of VLSI system performance. As technology progresses, VLSI on-chip interconnects encounter increasingly significant challenges, such as (1) signal attenuation and (2) crosstalk coupling. This paper proposes two analog/RF design techniques for high performance nanoelectronic on-chip interconnects: (1) application of distributed amplifiers for signal attenuation...
Network-on-chip (NoC), one of the most promising interconnection schemes for complex SoC design, presents large design space. Because the influence of different parameters on the performance of the NoC varies significantly, it is desirable to analyze and understand specific effect of these parameters on the overall performance in order to provide NoC designers guidelines to optimize their plans. In...
Clustered superscalar is an attractive alternative to large monolithic superscalar, and point-to-point (p-to-p) network is often used as inter-cluster communication networks (ICCN) to transfer dependent values between clusters. This new class of networks has demands and characteristics different from traditional networks. In order to pursue high performance, it should be highly coupled with the microarchitecture...
With the ever-increasing complexity and the cost on SoC??s verification, more attentions are paid to the hardware/software co-verification. In this paper, two HW/SW co-verification methods are compared between virtual-prototype machine and HW-board platform. A hardware platform on ARM-prototype system for an application-specific SoC??s HW/SW co-verification is implemented complied with software design...
A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by...
This paper presents a novel digitally controlled phase-locked loop (DCPLL) for SoC applications. The DCO of the DCPLL is designed by a flexible design method. By the method, a high performance of DCO can be implemented in a straightforward way. Finally, the DCPLL design is implemented by SMIC 0.18 ??m logic 1P6M CMOS technology. The area of the DCPLL is 0.08 mm2. The post-layout simulation results...
With the developing of the integrated circuit design and fabrication technology gradually, system-on-chip (SoC) technology has been widely used because of its high performance such as small size, low power consumption and so on. This paper describes a digital three-phase SPWM signal generation SoC based on OpenRISC1200, a 32-bit RISC processor core. The system integrates parameter controlling, displaying...
A single-inductor dual-output DC-DC converter designed in a 90 nm CMOS technology is presented in this paper. One of the sub-converters is a buck converter, and the other one is a boost converter. There are totally five power switches in the power stage. The values of the off-chip inductor and capacitors at the output of each sub-converter are 1 ??H and 1 ??F, respectively. The switching frequency...
This paper discusses an 8MHz square wave oscillator used for a clock signal of the digital core of a mixed signal integrated circuit (IC). The frequency is determined by a bias current that charges a capacitor until it triggers a comparator with a voltage reference as the second input. A low drop out (LDO) voltage regulator is used to supply the oscillator so that variations in the battery voltage...
With the development of IC technology, the commutation architecture has become a major bottleneck in Multi-processor System on Chip (MPSoC) design, which imposes communication based design into computation based design. It must provide enough bandwidth as well as the latency requirement. Network on Chip (NoC) has been considered as a new paradigm for its extensibility and power efficiency. This paper...
This paper discusses a novel RF Built-in-Self-Test (RF-BiST) targeting to replace the traditionally expensive and time-consuming RF parametric phase error test on a GSM/EDGE Digital Radio Processor (DRP) radio transceiver. The verification of the RF BiST in a production environment and a comparison of the internal BiST vs. the current test in are presented, which validates the RF BiST as an accepted...
A BIST scheme that can both characterize the dynamic and static parameters of ADCs in Mixed-Signal SoCs are proposed in this paper. This approach can be implemented almost all digitally except for a few simple analog filters. Analog stimulus for both the dynamic and static test are encoded and stored in on-chip RAM or ROM and retrieved when the corresponding test starts. Elemental operative units...
This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC??s static parameters can be estimated in shorter testing time with low hardware overhead...
In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output...
A novel programmable security processor for cryptography algorithms is presented in this paper. The 16-bit length RISC-like instruction set and 3-stage pipeline provide low code density, low hardware cost and low power consumption. Parallel on-chip lookup tables are integrated to obtain satisfactory performance of cryptographic processing. Chinese wireless local area network block cipher standard-SMS4...
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