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The presentation will discuss the future memory technologies beyond the 30 nm node, especially for DRAM, NAND Flash, new memories such as Phase change RAM (PRAM), and ferroelectric RAM (FRAM), and novel device structure technologies, which include how far we can extend so far successful conventional semiconductor memories. First of all, business demands and new applications of memories will be summarized...
The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation...
As CMOS scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full CMOS compatibility, such as Logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility...
A new paradigm for silicon memory technology is proposed. A technological breakthrough that will overcome the saturation in revenue obtained from `scaling??, a novel type of fusion memory is presented. A high-speed DRAM and non-volatile flash memory are integrated in a single memory transistor. The memory cell is named unified-random access memory (URAM), as multi-functional operation is processed...
A capacitor-less DRAM cell based on ferroelectric-gate memory transistor structure is introduced. Compared to the conventional DRAM cell, it offers much simpler cell structure, longer retention time, easier scaling, and lower power consumption. Cell size of 4F2 can be realized. It is also most suitable for embedded applications.
The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel...
Characteristics of inorganic and organic ferroelectric thin films are discussed from viewpoints of ferroelectric random access memory (FeRAM) applications. It has been found in BiFeO3 films formed by chemical solution deposition that the leakage current at high electric field decreases significantly by substituting Mn atoms for Fe atoms. In these films, well saturated hysteresis loops in P-E (polarization...
A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows...
SRAM, the important memory component, has been widely used in design of digital and communication circuits. SRAM is also an effective vehicle for process development and qualification due to its complexity and high density in which an engineer is able to detect the process issues. Generally SRAM??s yield is used as an indicator of the semiconductor nodes yield. In this paper we present the analysis...
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
This paper proposes a novel circuit architecture and its operation style for three-level ferroelectric random access memory (FeRAM) which can improve storage density by 1.5 times compared to traditional ITIC FeRAM under same technology. A new reference voltage generation scheme is adopted to enhance the reliability of this proposed circuit architecture. Based on the results of simulation, the function...
This study analyzed the effect on the bit-line voltage of imprint degradation in FeRAM. The hysteresis loop of the ferroelectric capacitor fitted by the three-line piecewise linear approximation model is proposed here to establish the relationship between bit-line voltage and imprint. Formulas are derived from this model for approximately calculation of the variation of bit-line voltage along with...
Bistable resistive switching of polycrystalline La0.67Sr0.33MnO3 (LSMO) thin films prepared by pulsed laser deposition (PLD) was investigated by applying voltage pulses with current compliance. Metallic LSMO films sandwiched by Ag and Pt electrodes show nonvolatile and reversible resistance switching behavior from a higher resistance state to a lower state with no data loss upon continuous readout...
This paper presents a cost-effective low power 45 nm bulk technology platform, primarily designed to serve the wireless multimedia and consumer electronics need. This technology platform features carbon co-IIP in the nMOS halo, laser annealing scheme, stress liner on the 45??-rotated wafer (<100>) for process simplicity to achieve high device performance and low leakage together. Drive current...
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early...
We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real...
In this paper, the advanced process has been presented to remove the WSix peeling which was brought in sub-100 nm DRAM SRCAT(sphere-shaped-recess-channel-array transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (chemical mechanical polishing) process.
For the new technology development, normal yield improvement methods useful to production are not enough. In the early phases, without yield signature, many systematic issues can not be captured by WAT or inline defect inspections. We need to create new analysis methods based on the technology development different phases. At the same time, multiple issues usually mix together and are not easy to...
One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used...
This paper presents a novel build-in-self-test (BIST) manufacture-oriented interconnect test strategy of SRAM-based field programmable gate arrays (FPGA). Programmable switches (PSs) and line segments are tested separately, which is different from previous methods. An improved depth-first-search (DFS) algorithm is developed for automatically deriving minimal or near minimal test configuration patterns...
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