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IC power consumption is not only a package thermal issue but also a significant and fast growing part of the world electricity consumption. A new low voltage transistor could contribute greatly to the need for a new Vdd scaling scenario. Green transistor (gFET) is based on tunneling and provides Ion and Ioff far superior to MOSFET at 0.2V if suitable low-Eg material is introduced into IC manufacturing.
Single-electron transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. And many researchers have proposed many logic units based on SETs. Through the analysis and simulation of the body-voltage effect of SET, for the first time, we propose a reconfigurable SET logic gate (RSETLG) based on the control of body-voltage...
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper...
In receiver, the output of demodulator is generally ??soft-bit?? signal in serial form. While the channel decoder implemented by analog circuits requires parallel decoder implemented by analog circuits requires parallel computation. To decrease the complexity and power consumption of analog decoder, the paper employs 0.6 ??m CMOS technology to design a two-level pipeline input interface circuit including...
This paper describes the design and implementation of a reconfigurable low power 180-nm CMOS cascade Σ-Δ modulator for multi-standard wireless communication. Both architectural and circuital reconfiguration is used to adapt its performance to multi-standard applications. Post layout simulation reveals that the prototype achieves 86.82/54.88/66.51d B peak signal-to-(noise+distortion) ratio within bandwidth...
A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp...
A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure...
Pseudo random bit generator is widely used in BIST for test pattern generation. Typical pseudo random bit generator adopts linear feedback shift register (LFSR) as its basic circuit. Dynamic LFSR (DLFSR[1]) which has better cryptographic properties with respect to typical LFSR consumes more power. This paper forwards a low power DLFSR (LDLFSR) circuit which achieves comparable performance with less...
It is well-known that shifting can replace a constant multiplication if the constant is a power of 2. We extend this idea in such a way that by employing more than 2 barrel shifters and a supplementary multiplier we can design a very efficient constant multiplier for general constants. With a support of variable precision computation, we can achieve high computational efficiency while maintaining...
This paper presents a power efficient reconfigurable correlator for DTMB channel estimation. In this design, a novel architecture based on fast Walsh transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit, the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost. Based...
Multi-threshold CMOS (MTCMOS) technology provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with MTCMOS technology. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest...
This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology,...
In large-scale system-on-chips (SoCs), the power consumption on the communication infrastructure should be minimized for reliable, feasible, and cost-efficient implementations. An energy-efficient network-on-chip (NoC) is necessary for application to high performance SoC design. Various low-power circuits are designed, and implemented in each open system interconnection layer. Low-swing serial link...
In this paper, we develop a novel way to achieve Mesh+Local Trees (MLT) flow in encounter. By blending the advantages of CTS and ClockMesh into one clock design flow, MLT is guaranteed to have smaller skew, and further optimize mesh structure to achieve lower power. MLT provides real loading sum value instead of estimating for global Mesh structure; another feature of this flow is that it provides...
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