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We report on the experimental evidence of a fully ballistic nano-FET with a voltage gain higher than 1 which is based on a 1D quantum ballistic conductor. In such a FET, the transconductance and the output conductance are basically modulated by the 1D subbands and the experimental results can theoretically be explained based on the Landauer-Buttiker formalism and the Buttiker model of the saddle-point...
For superluminescent diodes fabricated on the substrate with five 6 nm InGaAsP quantum wells and two 15 nm InGaAsP quantum wells, a very broad emission spectrum is obtained. The spectral width is nearly 400 nm, covering the range from 1250 nm to 1650 nm.
A differential low noise amplifier applied in ASK receiver is designed and fabricated in UMC 0.18 ??m CMOS process. The amplifier employs a differential cascode structure with source degeneration stage for single input and differential output, and avoids using balun when connected to mixer. This low noise amplifier has a measured forward gain of 18.2 dB and a noise figure of only 1.65 dB, thus can...
This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the...
A 260 MHz continuous-time 5th-order Gm-C biquad low-pass filter with an automatic tuning circuit is described. The Nauta??s transconductor is applied for high frequency design. The cutoff frequency tuning can be achieved by adjusting load capacitance in two ways. The filter cutoff frequency is 260 MHz. The HD3 is less than -50 dB for input signals up to 400 mVpp. The power consumption is 24 mW with...
A mobile TV tuner baseband for the newly established China Mobile Multimedia Broadcasting (CMMB) is presented. The baseband VGA achieves more than 40 dB gain tuning with temperature compensation. The baseband filter provides 0.5 dB passband ripple and 35 dB attenuation at 6 MHz with the cutoff frequency at 4 MHz. In addition, the calibration of filter is reported to achieve the bandwidth accuracy...
In this paper, a low-power CMOS variable gain amplifier (VGA) with dB-linear gain, which is based on an approximated exponential equation is presented. Being designed for GPS application, the proposed VGA is composed of two cascaded variable gain stages and a fixed gain stage, and has advantages of low-power, wide controlled-gain-range and highly-linear. The VGA is implemented in 0.18 ??m CMOS technology...
This paper describes the design of a polyphase filter in GSM receiver with low-IF topologies, using the circuit scheme of active-RC with the performance of single chip integrated. Based on TSMC 0.18 ??m CMOS process, the Spectre simulation results indicate that the filter is centered at 110 kHz with 200 kHz of bandwidth. It has a voltage gain of about 30 dB, an image rejection ratio of about 38 dB...
This paper presents an in-depth treatment of the theories and application of analog polyphase filters used in Bluetooth systems. Comparison is made among a variety of different filters with a focus on the active type. In addition, some practical design details will be identified and explained. The passive and active RC filters are fabricated in a 0.18 ??m CMOS process with 6 metals and 1 polysilicon...
In this paper, the opportunities and challenges of utilizing nanoscale CMOS technologies for application in medical ultrasound imaging applications are discussed. The paper focuses on the analog circuitry used for readout of ultrasound transducers in miniaturized systems where transducers and electronics are tightly integrated. It will be shown that systems that demand small parasitic capacitances,...
A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5 ??m CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded)...
In this paper, a programmable time-gain-compensation (TGC) amplifier dedicated to medical ultrasonic imaging systems is presented. This amplifier is composed of a true-logarithmic amplifier (TLA) and control circuitry. By using this amplifier, the early-returned strong echo signals from the near field tissue are less amplified, and the late-returned weak echo signals from the far field tissue are...
Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC??s 0.6 ??m CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function...
A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024??1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel...
This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity...
A module of genetic algorithms suitable for evolvement analog IC is designed, which don??t relate with specific physical circuits and has excellent transplant ability. With the help of the interface module, the module adapted well to evolvement analog filter circuits and wide band high gain amplifier etc to optimize their performance. Using SMIC 0.18 ??m CMOS mixed technology, a evolvement AGC amplifier...
In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology,...
An overview of the recent advances in digital-domain linearity enhancement techniques for multistep analog-to-digital converters (ADCs) is presented. Leveraging on increasingly more abundant on-chip processing, a built-in digital adaptability arises as the common denominator underlying most of these approaches. A multitude of the techniques are analyzed in this paper with the associated complexity,...
This paper presents an asynchronous 1 MHz DC-DC boost converter for TFT LCD power supply, using a pulse-width-modulated peak current mode controller. Both complete small signal analysis and overall efficiency investigation of the boost converter are performed, as well as the discussion of compensation method. An error amplifier with a compensation network and a sum-comparator with three input channels...
A 0.35 um BiCMOS dual-path, dual-differential sample-and-hold circuit is presented in this paper. The resolution of the circuit reaches 8 bits, and the sampling rate reaches 250 MSPS. The circuit features an alternate working mode, and reduces the circuit?? demand for speed. From simulation of the circuit, it can be found that SNR is 55.8 dB, that INL and DNL are smaller than that of 8-bit ADC, which...
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