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Continuous device scaling has led to the development of various transistors such as Ultra-Thin-Body SOI MOSFET, FinFET, and gate all around (GAA) MOSFETs . As the device shrinks further, the ultimate MOSFET structure would be GAA nanowire MOSFET with a fully depleted channel thoroughly controlled by the gate electrode. In this paper, fabrication processes of silicon nanowire MOSFETs on bulk Si using...
An overview of the science and technological aspects of Si-based nanodevices relevant to n+4 technology node and beyond is presented in this paper. Nanoscale CMOS and beyond-CMOS devices, based on innovative concepts, technologies and device architectures, are addressed.
In this paper, voltage transfer characteristic (VTC) of inverter based on Twin Silicon Nanowire MOSFETs (TSNWFETs) is extracted. TSNWFETs with 40 nm gate length and 10 nm nanowire diameter are used to construct inverter. Gain, switching threshold voltage, noise margin and transition width are extracted from VTC to show the performance of inverter based on TSNWFETs. In addition, these performance parameters...
In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account...
The transport characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with radius of 5 nm have been investigated. Mobility was estimated by extracting of source/drain resistance.
In this work, channel thermal noise in the twin silicon nanowire MOSFET (TSNWFET) is predicted using analytic thermal noise model taking into account short channel effects. TSNWFET used in this work has 40 nm gate length, 5 nm radius of silicon wire, and the 3.5 nm of gate oxide. Predicted thermal noise is compared with that of the planar MOSFET using various processes.
This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) n-type triple-gate FinFETs with high-?? dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is...
32 nm Si and Si1-xGex SOI Coplanar N Channel Vertical Dual Carrier Field Effect Transistors for mixed signal and communication applications are presented.
Mobility enhancement by strain is a critical element in today??s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials.
The physical mechanisms of electron mobility (??e) enhancement by uniaxial stress are investigated for nMOSFETs with surface orientations of (100) and (110). From full band calculations, uniaxial-stress-induced split of conduction band edge (??EC) and effective mass change (??m*) are quantitatively evaluated. It is experimentally and theoretically demonstrated that the energy surface of 2-fold valleys...
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed...
In this paper, an accurate and efficient one dimensional self-consistent numerical solution of <100> uniaxially strained n-MOS structure is presented based on finite element method. The solution is developed using FEMLAB considering wave function penetration effect into gate oxide. Significant change occurs in the eigen energies and the electron occupancies, intrinsic carrier concentration,...
A systematic study of the Schottky barrier lowering induced by dopant segregation during Ni and Pt germanidation is presented. Both investigated doping species, As and P, segregated at the germanide/Ge interface during germanidation due to the snowplow effect. The effective Schottky-barrier height at 0 K of NiGe/n-Ge reduced from 0.72 eV for diodes without ion implantation to 0.19 eV by As segregation...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
A quasi two-dimensional conduction model based on the thermionic emission of charge carriers over the energy barriers at discrete grain boundaries is proposed. The grain boundaries are characterized by an energy-dispersed density of trap states and a conduction model is formulated for a polycrystalline silicon thin-film transistor with an intrinsic channel. A ??line?? charge is formed adjacent to...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
Solvers based on a spherical harmonics expansion (SHE) of the Boltzmann equation (BE) are a deterministic alternative to the stochastic Monte Carlo (MC) method. Their numerical properties are very similar to the classical approaches (drift-diffusion or hydrodynamic models), and the same numerical methods can be used (box integration, maximum entropy dissipation scheme (MEDS), Newton-Raphson method,...
We present a characteristic function approach to parameter extraction for Si-based on-chip spiral inductors with a center tap. A closed-form analytical expression to extracting the model parameters specifically for the center tap branch is developed. The model parameters can then be extracted analytically. The validity of the present approach is verified by measurement based on 0.18 ??m CMOS process.
With the complementary metal-oxide-semiconductor (CMOS) technology approaching its scaling limit, many novel devices and material are being considered to enable further scaling of CMOS. Carbon nanotubes show unique properties and are currently considered as a potential alternative material for nano-CMOS building blocks. Performance of carbon nanotube field effect transistors (CNFET) can be competitive...
Practical aspects of synthesis and applications of single-wall and multi-wall carbon nanotubes (SWNT and MWNT, respectively) are presented. Among numerous potential applications, utilization of nanotubes for interconnections in microelectronics and in gas sensors is considered in more detail. The issues related to compatibility of nanotubes synthesis and manipulation processes with the Si planar technology...
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