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The presentation will discuss the future memory technologies beyond the 30 nm node, especially for DRAM, NAND Flash, new memories such as Phase change RAM (PRAM), and ferroelectric RAM (FRAM), and novel device structure technologies, which include how far we can extend so far successful conventional semiconductor memories. First of all, business demands and new applications of memories will be summarized...
In 2007, NAND flash memory was first introduced into the personal computing platform by Intel in the form of a non-volatile read/write cache to augment the PC computing platform memory subsystem. This innovation provided faster random access to key data and files instead of requiring access to the magnetic hard disk drive. In its introductory form, utilizing then available NAND flash memory generation...
Scaling limitations on NVM Stacked gate embedded into high-performance (HP) CMOS logic process will be reviewed with potential solutions identified. As technology continues its shrink path into 65 nm and beyond, scaling is becoming challenged due to the required high fields for write and erase (W/E) in stacked gate technology and the low leakage requirements for long term retention after cycling (RAC)...
A capacitor-less DRAM cell based on ferroelectric-gate memory transistor structure is introduced. Compared to the conventional DRAM cell, it offers much simpler cell structure, longer retention time, easier scaling, and lower power consumption. Cell size of 4F2 can be realized. It is also most suitable for embedded applications.
The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel...
A method to design CMOS-compatible diode-based One-Time Programmable (OTP) memory is discussed in this paper. In particular the program disturb problem is resolved by using diode drivers with sufficiently high breakdown voltage. The choices of memory elements and various available diodes in a standard CMOS process are carefully studied to obtain an optimal combination. Different memory cells were...
To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM...
This paper proposes a novel circuit architecture and its operation style for three-level ferroelectric random access memory (FeRAM) which can improve storage density by 1.5 times compared to traditional ITIC FeRAM under same technology. A new reference voltage generation scheme is adopted to enhance the reliability of this proposed circuit architecture. Based on the results of simulation, the function...
This paper presents a comparison study between double-switch (DS) and single-switch (SS) cross-coupled CMOS VCO architectures at 2 GHz and 16 GHz. The oscillators are designed with optimal differential tank oscillation amplitude, which is equal to the threshold voltage of the cross-coupled transistors. Measurement data from prototype oscillators show that the DS architecture can achieve a better performance...
A novel decoder for Complementary Code Keying (CCK) modulation is proposed in this work. Compared to the parallel decoder architecture based on Fast Walsh Transform (FWT), the presented pipelined architecture has better hardware sharing and utilization efficiency, as well as smaller area. Its hardware area for finding the maximum decoding output value is minimized by employing a low-complexity on-the-fly...
RFID tags have gradually become popular tools for identification of products. To ensure the secure information transaction of tags, a scheme of RFID system authentication protocol based on Elliptic Curve Cryptography (ECC) is proposed. However, hardware implementation of ECC processor for RFID tags is a challenge for the requirements of low-power consumption and low-cost chip resource. In the paper...
A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024??1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel...
A methodology for building a low-power high-capacity associative system has been developed. In the system, matching cells having bell-shaped I-V characteristics play the role of similarity-evaluation elements and can be replaced by nanoscale quantum-effect devices. The study is aiming to extend the current CMOS designs to the coming era of nano-devices. A multi-core/multi-chip architecture has been...
The security processor proposed in this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer, the processor can act as a bus master. This architecture improves the efficiency of system bus and reduces the burden of host CPU. Additionally, the proposed processor is connected to the system bus via a GALS Wrapper. Thus, high throughput can be achieved...
A new high compression compressor is proposed in this paper. This compressor has 7 inputs, 2 output, 2 carry-ins from adjacent two cells and 2 carry-outs to the next two cells. It achieves higher compression ratio than 4:2 compressor, 5:2 compressor and 6:2 compressor. Simulation shows that a 64x64 bit multiplier using this proposed 7:2 compressor is not only 16% faster than multiplier built with...
This paper proposes a unified, scalable dual-field Montgomery multiplier architecture which can operate in both prime GF(p) and binary extension fields GF(2n) for arbitrary prime numbers and irreducible polynomials. The Montgomery multiplier architecture has advantages in speed and flexibility for operator size compared with conventional architectures using long adders or long-bit ?? short-bit multipliers...
With the developing of the integrated circuit design and fabrication technology gradually, system-on-chip (SoC) technology has been widely used because of its high performance such as small size, low power consumption and so on. This paper describes a digital three-phase SPWM signal generation SoC based on OpenRISC1200, a 32-bit RISC processor core. The system integrates parameter controlling, displaying...
With the development of IC technology, the commutation architecture has become a major bottleneck in Multi-processor System on Chip (MPSoC) design, which imposes communication based design into computation based design. It must provide enough bandwidth as well as the latency requirement. Network on Chip (NoC) has been considered as a new paradigm for its extensibility and power efficiency. This paper...
It is well-known that shifting can replace a constant multiplication if the constant is a power of 2. We extend this idea in such a way that by employing more than 2 barrel shifters and a supplementary multiplier we can design a very efficient constant multiplier for general constants. With a support of variable precision computation, we can achieve high computational efficiency while maintaining...
To deal with nowaday multi-standard audio and video processing, a heterogeneous multi-core SOC architecture is presented in this paper, which is composed of a general purpose RISC processor, an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding, an efficiency and flexible HW/SW cooperating architecture is...
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