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With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold...
A low power monolithic reconfigurable direct-conversion receiver RF front-end for 802.11a/b/g applications is presented. It consists of a reconfigurable LNA and a high linearity quadrature down-converter. The LNA could be switched between two operation bands by utilizing a fully-differential switchable inductor. With a positive feedback, the noise figure of the common gate LNA is lowered down. The...
A differential low noise amplifier applied in ASK receiver is designed and fabricated in UMC 0.18 ??m CMOS process. The amplifier employs a differential cascode structure with source degeneration stage for single input and differential output, and avoids using balun when connected to mixer. This low noise amplifier has a measured forward gain of 18.2 dB and a noise figure of only 1.65 dB, thus can...
This paper presents a technique using current-mode approach for a CMOS differential low noise amplifier design, simulated with a TSMC 0.18 ??m RF CMOS process, working at 1.2 V supply. A comparison with conventional voltage-mode LNA shows that this LNA has advantages of low voltage, low power consumption and simple structure. Simulation results demonstrate that at 2.4 GHz, the noise figure is only...
An RF Transmitter front-end implemented in 0.18 μm CMOS for WiMedia MB-OFDM UWB is presented in the paper, which consists of a V-I converter, an up modulator, a Differential to Single (D2S) converter, a PA and the divided by 2 divider for the LO carrier generation. The post simulation shows the maximum transmitter linear output power level of -2 dBm (3.1-4.8 GHz band) with 6 dB power control range,...
In this paper, a 1.2 V low-power CMOS current-reused voltage-controlled oscillator (VCO) for IEEE 802.16e is presented. Two drain resistors are used to improve magnitude symmetry of output signals. The design is based on the TSMC 0.18 ??m mixed signal/RF process. The output frequencies range from 2.39 GHz to 2.21 GHz with the controlled voltage from 0 V to 1.2 V. The measured output power is -4.2...
With a simple analysis of phase noise in voltage-controlled oscillators, a 2.4 GHz CMOS LC VCO is designed in 0.18 ??m CMOS technology. The proposed VCO uses three filters to remove noise from the tail current source, the reference current source, and the output node of VCO core. The VCO has a tuning range from 2.29 GHz to 2.59 GHz, while the VCO core draws 3 mA of current from 1.8 V power supply...
A 3rd order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 ??m standard CMOS technology. The complex filter is centered at 4.092 MHz with bandwidth of 2.4 MHz. The in-band 3rd order harmonic input intercept point (IIP3) is larger than 19 dBm, with 50 ?? as the source impedance. The input referred noise is about 80 ??Vrms. The RC tuning...
Based on the 4-channels neural signal regeneration system which was realized by using discrete devices and successfully used for in-vivo experiments of rats and rabbits, an integrated circuit (IC) with 6-channels of neural signal regeneration has been designed and realized in CSMC??s 0.6 ??m CMOS technology. The IC consists of a neural signal amplifier with adjustable gain, a buffer stage, and a function...
This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity...
In receiver, the output of demodulator is generally ??soft-bit?? signal in serial form. While the channel decoder implemented by analog circuits requires parallel decoder implemented by analog circuits requires parallel computation. To decrease the complexity and power consumption of analog decoder, the paper employs 0.6 ??m CMOS technology to design a two-level pipeline input interface circuit including...
On-chip interconnects form the bottleneck of VLSI system performance. As technology progresses, VLSI on-chip interconnects encounter increasingly significant challenges, such as (1) signal attenuation and (2) crosstalk coupling. This paper proposes two analog/RF design techniques for high performance nanoelectronic on-chip interconnects: (1) application of distributed amplifiers for signal attenuation...
A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure...
In this paper, we present a non-volatile register based on hybrid Spintronics/CMOS technology, which can store securely and non-vocatively all the intermediate data in the logic circuits as FPGA and ASIC. The non-volatility of this register allows to power down the circuits keeping the data thereby reduce significantly the standby power and accelerate the chip re (boot) latency. Based on STMicroelectronics...
The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below, causing strong layout-dependent proximity effects. Photolithography, strain silicon engineering, and ion implantation are the primary causes of those effects, whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly...
Metal MEMS structures can be formed by metal electroplating with the aid of thick-photoresist molds. The microfabrication features low-temperature process that is post-CMOS compatible and can be used for on-chip integration of high-performance RF parrives for RFICs. On the other hand, The plating process can be combined with silicon micromachining techniques to build operation tools, like probe-cards,...
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