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In this paper, a novel device - MOS-NDR transistor is proposed and fabricated which is composed of four N-channel metal-oxide-semiconductor field effect-transistor (NMOS) devices. This MOS-NDR transistor could exhibit the negative differential resistance (NDR) characteristics similar to the conventional NDR device such as compound material based RTD (resonant tunneling diode) in the current-voltage...
Mobility enhancement by strain is a critical element in today??s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials.
In this paper, electrostatic discharge (ESD) protection in advanced technologies is discussed. The dilemma of ESD protection in advanced technologies and whether we will maintain the need, and desire to provide ESD protection in the future will be reviewed. This issue will influence the direction of the field of ESD protection and the ESD Technology Roadmap. The paper will also focus on what will...
Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on the physical understanding of circuit aging effects, we develop a predictive short term and long term model to characterize NBTI-induced threshold voltage degradation (??Vth) at transistor level. Due to process...
The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65 nm CMOS process. STI-induced stress effect, well proximity effect, as well as HCI and NBTI reliability effects, which can not be neglected for technologies beyond 90 nm and must be properly modeled for accurate circuit simulations, are discussed in this study.
The piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced stress in CMOS technology. However, many reports show it failing at the high levels of strain needed for future technology generations. This is because an approximation is made which is only valid for very low stress levels. The piezomobility formulation removes this approximation in...
This paper reviews the measurement and modeling issues of the channel thermal noise in MOSFETs as a result of the aggressive reduction of the channel length into the sub-100 nm regimes. It also shows the noise performance of devices in 65 nm CMOS technology.
To date, electronics uses electron charge as a state variable which is often represented as voltage or current. In this representation of state variable in today??s electronics, carriers in electronics devices work independently even to a few and single electron cases. As the scaling continues to reduce the feature size, power dissipation and variability become two major challenges among others as...
The current status of SOI technology using wafer bonding is reviewed and its technological positioning in CMOS scaling is discussed. While bulk CMOS technology is encountering various kinds of critical issues, SOI technology using wafer bonding provides unique solutions by virtue of its flexible material design. Mobility enhancement through strained-SOI (sSOI) or optimization of crystal orientation...
A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) is designed and fabricated with standard 0.35 ??m CMOS technology. This OEIC circuit consists of light emitting diodes (LED), silicon dioxide waveguide, photodiodes and receiver circuit. The silicon LED operates in reverse breakdown mode and can be turned on at 8.5 V 10 mA. The silicon dioxide waveguide is composed of multiple layers...
Four years ago [1] we assessed the status of CMOS imaging for high-speed applications. We also gave an outlook of the near future in high-speed imaging. In this paper we revisit the topic of high speed imaging in a slightly different angle and make the point of recent developments in the field, with emphasis to bioimaging applications.
This paper reports the comparison between conventional ash followed by wet bench process approach and the new all wet process for LDD implant application. The comparison covers the areas of defect performance, (material loss, electrical data, yield) and chemical consumption.
Most of papers have ignored the effect of gate-drain capacitance of transistor due to its complexity when they analyze a low noise amplifier circuit (LNA). However, as scaling down the CMOS technology, the ratio of gate-drain capacitance (Cgd) to gate-source capacitance (Cgs) increases. This phenomenon affects the input matching, power gain and noise figure of the LNA circuit. In this paper, we propose...
In this paper, design approach of 2.4 GHz CMOS ultra low power Low Noise Amplifier (LNA) using 65 nm CMOS technology is presented. Conventional Inductively degenerated cascode topology where both MOS transistors are biased in sub-threshold region is used. There are many performance factors of LNAs such as signal power gain, noise factor, input referred 1-dB compression point (P-1dBin) and power consumption...
A high linearity flat conversion gain down-conversion mixer for 3.1˜4.9 GHz Ultra-wide Band (UWB) receiver is presented in this paper. The mixer is designed based on Gilbert cell. It adopts source degeneration resistors and current injection method to improve the linearity. Shunt-peaking technique and tuning inductors are used to flat conversion gain. Designed and fabricated with SMIC 0.18 μm CMOS...
A bi-quadrature down-conversion mixer with improved topology from 6 GHz to 9 GHz for MB-OFDM UWB application is presented in this paper. The mixer improves conversion gain of previous similar construction a lot and demonstrates a conversion gain of 14.0˜14.8 dB, Noise Figure (NF) of 15.1˜17.0 dB, and IIP3 of -15.0˜-13.9 dBm. The power dissipation is 19.8 mW under a supply voltage of 1.8 V in 0.18...
An ultra low power, low cost, 1st-order derivative Gaussian pulse generator for 3.1 GHz-10.6 GHz impulse-radio carrier-free ultra wideband (UWB) transmitter was designed and fabricated in commercial 0.13 μm CMOS technology. The pulse generator integrates three cascade stages to generate square waveform, Gaussian pulse waveform and 1st-order Gaussian derivation waveform, respectively. The UWB impulse...
Ultra-short Gaussian monocycle pulses (GMP) of 280 ps pulse width, -20.2 dB ringing level and 3.6 GHz center frequency were generated in 0.18 μm CMOS in which meander dipole antennas were integrated for impulse radio based ultra-wideband transmitter system. The transmission and reception of the generated GMP in the CMOS chip and between the chips by use of the integrated meander dipole antennas were...
This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the...
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