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An overview of the recent advances in digital-domain linearity enhancement techniques for multistep analog-to-digital converters (ADCs) is presented. Leveraging on increasingly more abundant on-chip processing, a built-in digital adaptability arises as the common denominator underlying most of these approaches. A multitude of the techniques are analyzed in this paper with the associated complexity,...
A 8-b 125 MS/s pipelined analog-to-digital converter (ADC) used in DVB-S2 is presented in this paper. Based on reviewing low-power design techniques of high speed ADCs, several technologies are used in the design including the SHA-less architecture to reduce the power dissipation significantly. Detailed analysis is given about the relationship between the closed loop bandwidth (BWclose) and the current...
An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.
A 0.35 um BiCMOS dual-path, dual-differential sample-and-hold circuit is presented in this paper. The resolution of the circuit reaches 8 bits, and the sampling rate reaches 250 MSPS. The circuit features an alternate working mode, and reduces the circuit?? demand for speed. From simulation of the circuit, it can be found that SNR is 55.8 dB, that INL and DNL are smaller than that of 8-bit ADC, which...
Based on the preamplifier-latch theory, a new topology structure of ultra high-speed comparator with low offset voltage applied to ultra high-speed A/D converters, which is composed of a preamplifier that includes a positive and negative resistance connected in parallel as its load, a regenerative latch and a simple output stage, is proposed. The method to analyze the speed and input offset voltage...
A 12-bit 20 MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp...
A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure...
A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage...
This paper presents an improved latched comparator which is suitable for high speed folding and interpolation ADC. The proposed comparator minimizes the kick back noise while regenerates the analog input signals. Injection reducing switch is introduced to suppress clock feedthrough and charge injection error. Transistors in common-gate arrangement are inserted to reduce kick back noise. Simulated...
Bootstrapped switches are used in a variety of applications such as pipelined analog-to-digital converters and high voltage switches, and drivers. This paper proposes a novel bootstrapped switching scheme for rail-to-rail sampling circuit. The implemented switch using new scheme can sample full-spread (0-5 V) signals under 5 V supplies. The new switch well eliminates the standard CMOS bulk effect,...
In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential...
This paper studies the error of the hybrid filter banks (HFB) due to analog realization errors. Small errors have a dramatic influence on the aliasing and distortion functions of HFB. The performance deteriorates with the error of analog devices growing. The simulations show that the aliasing and distortion errors based on power complementary pairs (PCP) are much lower than conventional HFB ADCs??...
An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.
A BIST scheme that can both characterize the dynamic and static parameters of ADCs in Mixed-Signal SoCs are proposed in this paper. This approach can be implemented almost all digitally except for a few simple analog filters. Analog stimulus for both the dynamic and static test are encoded and stored in on-chip RAM or ROM and retrieved when the corresponding test starts. Elemental operative units...
This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC??s static parameters can be estimated in shorter testing time with low hardware overhead...
In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output...
A new digital pressure-sensing device is presented. It employs the Micro-ElectroMechanical Systems (MEMS) technologies to form pressure sensing using PMOS ring oscillators to generate frequency which depends on the pressure-induced stress. The digital pressure sensor has several advantages. One of them is to convert the analog measurement of pressures into the frequency measurement. Compared to a...
This paper presents a bulk micro-machined single axis accelerometer with analog signal conditioning circuit on a single chip. Design advantages include combining electrical isolation structures and mechanical connection structures with insulating materials refilled trenches to increase transducer sensitivity by minimizing parasitic capacitance, and lower package cost due to post-CMOS process. Several...
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