The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As complexity in automotive semiconductor applications is increasing, the need for robust and failure free semiconductors is increasing even more. This paper addresses the special requirements of automotive applications. The operating conditions of semiconductors in a car will be shown. The differences to other challenging semiconductor applications will be pointed out. It shows, that automotive application...
Fraunhofer IZM introduced a 3-D integration process, the so-called ICV-SLID technology based on inter-chip vias through the device substrates (through silicon vias) and metal bonding using solid-liquid-interdiffusion (SLID) soldering for simultaneous mechanical and the electrical connection [1]. The ICV-SLID technology is optimized for 3D integration of e-CUBES processing units, while interconnection...
We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy...
A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal...
Experimental μ-Raman spectroscopy (μRS) results are used to determine the appropriate plastic yield criterion for an accurate finite element modeling of stress in and near copper filled through-silicon-vias (TSV). It is found that the strain-hardening yield criterion gives the most accurate correlation between the ??RS results and the finite element modeling. The verified yield criterion is used to...
Electromigration is a well-known root-cause for long-term reliability problems. This paper demonstrates that the resistance to electromigration is significantly increased when solder-based intermetallic bonding is used as an alternative to standard solder flip-chip interconnections. Two different intermetallic joint-types are investigated: Cu-Sn and Co-Sn. After 1000h, no failures or degradation mechanisms...
This article reports novel copper seed layers containing dilute Ru or RuNx for the barrierless metallization. Based on XRD, FIB, TEM, resistivity and leakage current measurement results, we conclude that copper does not react with Si up to 680??C for 1 hour when the Ru-or RuNx-bearing seed layer is directly in contact with the barrier-free Si. Our results shed lights on the possibility of using these...
A porous pSiCOH interconnect dielectric with a dielectric constant k=2.4 has been developed from mixtures of a SiCOH skeleton precursor and bicycloheptadiene (BCHD) and optimized for successful integration in the interconnect structure of 45 nm ULSI chip. The ulk pSiCOH is characterized by small pores, low pore connectivity, and excellent electrical properties. This paper describes the selection of...
A mechanistic study of CO2 plasma damage to OSG (organosilicate glass) low-k films was performed using both inductive-coupled ICP and capacitive-coupled RIE sources with varying plasma energy and density. The nature of the damage was investigated using spectroscopic ellipsometry (SE), Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectrometer (XPS), and capacitance-voltage (C-V)...
A self-aligned air gap interconnect structure with sidewall reinforcement is developed. The new structure lowers the capacitance of 0.09um/0.09um (w/s) metal wires by as much as 25%, and exhibits low leakage current. As compared to un-protected air gaps, the structure also greatly improves the electromigration resistance and the misalignment margin for unlanded vias. Furthermore, the sidewall protection...
A three dimensional integrated circuit (3DIC) integration flow, process and electrical results are reported. Well-controlled high aspect ratio (AR=8:1 and AR=15:1) through silicon vias (TSVs) were successfully filled with both copper (Cu) and tungsten (W). Metal to metal diffusion bonding was demonstrated with good uniformity and resulted in good electrical performance. For the first time, a cost...
In this paper the process integration challenges for a 3-D die to wafer stacking technology are investigated. A process for etching through the full multi layer field dielectric of a completed wafer is achieved. Ionized PVD is used to form a barrier and liner, and is shown to allow full metal coverage of scallops and undercut resulting from the combined deep silicon via etch and oxide liner deposition...
Current-carrying capacity of carbon nanofibers (CNF) is investigated for potential interconnect applications. The measured maximum current density in the suspended CNF in air is inversely proportional to nanofiber length and independent of diameter. This relationship can be described with a heat transport model that takes into account Joule heating and heat diffusion along the CNF, assuming that breakdown...
The simultaneous formation of Cu/Sn microconnects and an adhesive bond during wafer level thermal compression bonding was evaluated using a 3D enabled single metal level test die and wafer. The wafer level bond process relied on locally dispensed adhesive to fix the dice to the wafer prior to bonding and to become a permanent bond during the bonding process. The die-to-wafer microconnect resistance...
Voltage ramp dielectric breakdown (VRBD) and time-dependent dielectric breakdown (TDDB) characteristics of ~40nm-wide Cu/SiO2 interconnect dielectrics were investigated. The addition of a SiH4 treatment before capping SiN deposition led to more uniform breakdown fields, and better TDDB performance. The integration of a Ti-based barrier resulted in the best uniformity of breakdown fields, and a dramatic...
Interconnect solutions for advanced technology nodes using PECVD techniques for low-k deposition require the use of porogen-based process with post deposition UV cure. By using two different UV cure lamps (A, B) in combination with different porogen loads, three different micro-porous low-k films are developed: Aurora?? ELK HM (k~2.5; porosity (P) ~25%), Aurora?? ELK A (k~2.3; P~34%) and Aurora??...
We have developed highly reliable low resistance copper contact technology for CMOS device beyond 32nm node. Cu contact is expected to reduce contact resistance but degradation of device performance caused by Cu diffusion into Si and filling failure of high aspect ratio contact hole using current BEOL Cu process are concerned. The excellent Cu diffusion barrier endurance of CVD TiN/PECVD Ti stacked...
The change in leakage I-V characteristics by multilevel processing of Cu interconnects with porogen-type p-SiOC (k=2.4) was investigated. Although the change can be eliminated by UV-cure condition, it was found that another process conditions can affect the leakage characteristics; the combination of NH3 plasma treatment after Cu-CMP and the additional UV-cure in multilevel process. It was also found...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.