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SOI technology has taken power/performance benefits of CMOS beyond those of bulk-CMOS technology in the arena of high-performance applications, including 4.7 GHz dual core Power 6 IC, PowerPC, and game processors. At the 45 nm node we have expanded the menu of devices offered in SOI technology to include general purpose applications, including ASICs and low power products. A spectrum of memory solutions,...
We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high tensile-stressed UV film in conjunction with stress memorization techniques (SMT). For the first time we demonstrate that using a UV-cured tensile film allows a 6% performance boost on the SOI NMOS, achieving a drive current of ~1170 muA/mum (1250, non-self-heated)...
In PD-SOI the oxide layer between MOSFETs and the underlying silicon substrate presents a thermal resistance that can lead to significant temperature rise for power dissipating devices. This can impact circuit performance and also introduce differences between device characteristics measured under DC conditions and those experienced under "at speed" operating conditions with low duty cycles...
Thin film SOI is a key technology for wireless and RF applications. We demonstrate the successful transfer of a DriftMOS transistor from the 130 nm technology to the 65 nm one on thin SOI. The process option introduced in this node enables to achieve high device performance: due to the new well patterning strategy, the main transistor figure of merit is improved.
Flexfet is a new SOI IDG-CMOS technology with a damascene metal top gate and an implanted JFET bottom gate that are self-aligned in a gate trench. The independent top and bottom gates are contacted at opposite sides of the channel by a local interconnect that is embedded in the isolation region between devices. A simple analytical dynamic threshold voltage model is developed and verified by extensive...
SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing...
Based on 3D numerical simulations and on a technological evaluation, we demonstrate the relevance of a new stacked nanowires architecture concept with independent gates, the PhiFET. We study the coupling effects in nanowires controlled by two independent gates. This architecture, proposed for low-power applications, reveals an excellent control of short-channel effects and improved ION/IOFF ratios...
With each new technology node the challenges of building a robust, scalable embedded memory grow. This trend drives higher process complexity and cost as well as increased capital equipment investments to support the process. In this study, the zero capacitor RAM (Z-RAM) [A SOI Capacitor-less IT-DRAM Concept, Okhonin, Nagoga, Sallese, Fazan, 2001 IEEE International SOI Conference, pp.153-154.] scalability...
An advanced partially-depleted (PD) silicon-on-insulator (SOI) CMOS device was optimized with full consideration of the floating body effect (FBE) using channel and S/D engineering. By adjusting channel and S/D implants' species and dosage, the S/D doping profiles across transistor sidewall junction will be shown to reduce floating body effects and sidewall junction capacitance. Reduced sidewall junction...
This paper presents the design and the behavior vs. temperature of RF antenna switches in a 130 nm SOI technology. The design is implemented using two types of transistors; floating body and body tied transistors. It is shown that the floating body transistor is the best candidate for the design of RF antenna switches implemented in a fully integrated RF communication system. Outstanding high temperature...
In this paper, we present active and passive performances of the 65 nm LP SOI HR technology from STMicroelectronics and two simulated circuits to illustrate the potentiality of the technology for millimeter wave (mm-wave) applications. 65 nm low power (LP) partially depleted (PD) n-MOSFET floating body (FB) shows a f/fmax of 160/200 GHz. Coplanar waveguides (CPW) present a measured attenuation constant...
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