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To achieve the required drive performance for sub 32 nm technology nodes there is strong interest in exploring the use of Ge-based technologies. This paper reviews some important processing aspects from a defect control viewpoint. Attention is given to crystal growth, shallow junction formation and germanidation techniques, respectively. The main focus is on defect related aspects. The last section...
Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence, as well as the high Rext issue for (110) PMOS are...
This presentation gives an overview of the requirements of the photonic components in their insertion in applications such as CATV, antenna remoting and base station connections in wireless communication systems. While the driving force for their use is bandwidth, the eventual limiting factors would be cost and reliability. The presentation reviews the advances in the state-of-the-art photonics devices...
The threshold voltages (Vth) of the double/triplegate bulk FinFETs implemented on bulk silicon wafers were modeled systematically and compared with data obtained from 2-D or 3-D device simulation. The Vth modeling of the bulk FinFETs was performed by considering charge-sharing, top corner effect, and surface potential lowering. The model predicted the Vth behavior with fin body thickness, body doping...
As device dimensions shrink to the molecular scale, theory and modeling assume an ever greater role. The analytical ability to experimentally determine the chemistry and geometry for individual molecular devices does not yet exist. Heroic experiments can be required to fabricate devices at this scale. Theory and modeling can relatively quickly explore the effect of the microscopic chemistry and geometry...
A generic double-gate (DG) MOSFET follows a generalized voltage equation from the first integral of Poisson equation and Gauss' law applied at the two gates, which is implicit and, in general, non-integrable when the silicon film is doped. Only DG with undoped body can be solved with implicit surface-potential solutions, or approximate surface-potential solutions for doped symmetric-DG (s-DG) structures...
This paper reports the modelling the gate tunneling current effects of sub-100nm NMOS devices with an ultra-thin (1nm) gate oxide. As verified by the experimentally measured data, the compact gate tunneling current model considering the distributed effect provides an accurate prediction of the gate, source, and drain currents for the device biased in triode and saturation regions. Based on the compact...
Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (HH-LVTSCRs) for Electrostatic Discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections...
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