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A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability...
In this paper, SONOS type FinFET device has been fabricated and characterized for the NAND flash application. Pre- and post-cycling characteristics are mainly studied both for the FinFET and planar device, with respect to the memory cell performance and device reliability. It has been demonstrated that the performance improvement of the FinFET is maintained after cycling stress, and most importantly,...
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (single-crystal Si layer stacking) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on the bulk to double the memory density without increasing the chip size. The feasibility of the technology was proven by the successful operation of 32...
A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line
Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell Vth distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectric of gate spacer such as oxide and air gap in 1Gb NAND flash memory
Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaVth = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack...
The advances in silicon technology that have been the backbone of tremendous previous growth, was foreseen in 1965 when Gordon Moore published his famous prediction about the constant growth rate of chip complexity. And, in fact, it has repeatedly been shown that the number of transistors integrated into silicon chips has indeed doubled every 18 months. Increases in packing density, according to Moore's...
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