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Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve fT/fMAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with fT/fMAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology...
A high density GMR sensor array was integrated with a standard CMOS chip for DNA hybridization detection. Absorption of magnetic nanoparticles by the hybridized DNA alters the sensor resistance, and generated electrical signals are directly measured with the on-die circuitry. The proposed biochip can be applied to other bio-reaction detection, e.g. protein assay, through different surface modifications
We present an advanced CMOS integration scheme based on embedded SiGe (eSiGe) with a novel graded germanium process. The retention of channel strain enabled a pFET performance gain of 15% over a non-graded eSiGe control. When combined with a compressive stress liner (CSL), the pFET drive current reached 770muA/mum at Ioff = 100nA/mum with VDD = 1V. Competitive nFET performance was maintained. Parasitics...
The authors demonstrate a novel CMP-less FUSI integration scheme which uses a spin-on sacrificial material for planarization showing 45nm gate length Ni-rich FUSI pMOS and NiSi FUSI nMOS transistors on HfSiON. This new scheme does not require CMP but remains compatible with phase-controlled dual-WF CMOS with independent silicidation of the S/D and the gate. This approach uses very selective dry etch...
Three- and four-level matrices of 15 times 70 nm Si Nano-Beams have been integrated with a novel CMOS gate-all-around process (GAA) down to 80 nm gate length. Thanks to this 3D-GAA extension of a Finfet process, a more than 5times higher current density per layout surface is achieved compared to planar transistors with the same gate stack (HfO 2/TiN/Poly-Si). For the first time, several properties...
The authors report novel 1000degC-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good Phim-eff of 5.08 and 4.24 eV, low Vt of -0.10 and 0.18 V, high mobility of 84 and 217 cm2/Vs at 1.6 nm EOT, and small 85degC BTI <20 mV (10 MV/cm for 1 hr) are measured
Low temperature device operation at 240 - 300 K temperature range is a promising approach to extend the device technology. The guideline of device design for cooling CMOS and the optimum operation temperature considering total power consumption is discussed for the first time. Also, the compatibility of cooling CMOS with advanced high-k gate dielectrics and embedded SiGe S/D technique are clarified
A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current...
An effect of fluorine incorporation into HfSiON on 1/f noise is shown for the first time. Fluorine effect on 1/f noise for SiON and HfSiON devices differ in that F does not improve the HfSiON N-FET 1/f noise. Apparently, the interface traps created by Hf close to the conduction band cannot be passivated by fluorine. For future analog/mixed -signal applications, HfSiON P-FET is expected to limit noise...
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
This paper describes a novel RF CMOS-MEMS switch that integrates RF MEMS switches and CMOS control circuits. A single-pole 8-through RF CMOS-MEMS switch was fabricated and its operation at 3.3 V supply voltage was achieved. The switch was encapsulated with a thin film at wafer level to prevent destruction during packaging. Experimental results confirm that the switch has mechanical reliability for...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6...
Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift...
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
Starting with the 45 nm node, a tradeoff between performance and density exists that become more severe at the 32 nm node. An in-depth analysis of the impact of pitch and increased parasitics on device performance in the 32 nm node is presented. To counteract these effects, reduction of parasitics, gate length scaling, and aggressive stress engineering are necessary. Optimized layout using a "relaxed-pitch"...
It is reported for the first time that the anomalous gate edge leakage current in NMOSFETs is caused by the lateral growth of Ni silicide toward the channel region, and this lateral growth is successfully suppressed by the control of the Ni silicidation region using the Si ion implantation (Si I.I.) technique. As a result, the anomalous gate edge leakage current is successfully reduced, and the standby...
This paper introduces the capacitive bulk acoustic wave (BAW) silicon disk gyroscope. The capacitive BAW disk gyroscopes operate in the frequency range of 2-8MHz, are stationary devices with vibration amplitudes less than 20nm, and achieve very high quality factors (Q) in low vacuum (and even in atmosphere), which simplifies their wafer-scale packaging. The device has lower operating voltages compared...
Wafer scale nanostencil lithography is used to define 200 nm scale mechanically resonating silicon cantilevers monolithically integrated into CMOS circuits. We demonstrate the simultaneous patterning of ~2000 nano-devices by post-processing standard CMOS wafers using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies around...
The authors demonstrate a novel 6.6% high-efficiency CMOS compatible piezoelectric aluminum nitride (AlN) thin-film based integrated β-radioisotope-powered electro-mechanical power generator (IREMPG). the authors integrate silicon betavoltaics with radioisotope actuated piezoelectric unimorph converters to efficiently utilize both kinetic energy and charge of the emitted beta particles for electrical...
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