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The authors present for the first time the full integration scheme and 512Mb product data for a trench DRAM technology targeting the 58nm node. The key technology enablers such as an extended U-shape cell device (EUD), high performance support devices, trench capacitor with metal-insulator-silicon (MIS)/high-k dielectric and metal-in-collar (MIC), and low-k inter-level dielectric (ILD) are demonstrated
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes a low-leakage 2.2-nm gate oxide pass transistor and a deep trench capacitor. A trench side wall spacer process enables a simplified collarless process. Connection to the buried plate is realized by silicided...
Floating gate interference resulting from capacitive coupling through parasitic capacitors surrounding the floating gate degrades the cell characteristics such as current, speed and cell Vth distribution. For the first time, we have introduced the cell characteristics improved using low-k dielectric of gate spacer such as oxide and air gap in 1Gb NAND flash memory
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