We present a hardened RTL processor core based on Leon2. Modifications are done at RT-level to achieve high configurability in an early stage of the development process. The main parts of the processor core can be protected against Single Event Upsets and Single Event Transients. Results and tradeoffs are presented and discussed
We quantify the SEU rate induced by neutrons in current devices, from both low energy (thermal) and high energy neutrons. New measured SEU cross sections from both kinds of neutrons in SRAMs, DRAMs and microprocessors are included
A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEU soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET...
The PHISco simulation tool was known to be able to predict the SEU cross section for incident ions. This tool is improved in this work to also predict the MCU rate. Experimental and predicted results are shown to be in good agreement on a 90 nm bulk SRAM. The simulated SRAM structure includes the N-well, which is known to be a barrier to the charge carriers.
We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and add appropriate system-level recovery and redundancy.
Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter –the word-line voltage margin ()– and the measured circuit alpha-SER. Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique proposed is based on correlating the ...
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