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A high order curvature-compensated CMOS bandgap voltage reference(BGR) is presented in TSMC 0.35μm CMOS technology with low power low temperature-coefficient(TC) and high power supply rejection ratio(PSRR). The design is used in low dropout regulators which is applied in implanted chips. TC is compensated by adjusting resistor ratio which have different temperature characteristics. A PSRR enhance...
A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors...
Due to process variations at the very low technology nodes, the manufactured chips are grouped into different speed bins. Currently, various types of maximum operation frequency (Fmax) tests are performed for efficient speed binning by applying complex functional or structural test patterns, which incurs high test cost. In this paper, a novel on-chip Binning Sensor is proposed which can monitor the...
Among power generation, transmission and use, distribution is an extremely important link. The distribution system includes a transformer and a variety of high and low voltage electrical equipment, the circuit breaker is a large amount of electrical appliances. The circuit breaker can be used to distribute electric energy, the asynchronous motor is not frequently started and the power line and motor...
The iterative property of inverse butterfly permutation network makes it possible to implement shift operation with simple routing algorithm, which has high application value in cryptography, digital image processing and other fields. Based on the inverse butterfly network, this paper proposes a subword shift unit, which integrates the operations of subword rotation shift, subword logical shift and...
A simulation method of non-uniform interface charges in pMOSFETs was presented in this paper. By using the 2D device simulation software, it increases the non-uniform interface charges array and calculation module. Bonded with the device negative bias temperature instability NBTI (Negative Bias Temperature Instability) degeneration model, the pure bias NBTI (Pure Drain Bias NBTI) degradation impact...
This paper presents a low-power all-digital first-order single-bit delta-sigma time-to-digital converter (TDC) with a differential bi-directional gated delay line time integrator. The differential time integrator features low power consumption accredited to the use of only one bi-directional gated delay line in performing time integration, full compatibility with technology scaling, rapid time integration,...
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