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The underlying variability in the ReRAM device operation, while undesired in many applications, can be advantageous for hardware security primitives. ReRAM devices also come with the advantage of having non-linear multi-state operation. By comparison with previous reported ReRAM PUFs, which utilized spatial variations in the devices' binary ON/OFF states, we proposed to use sneak path currents and...
We present a study on multi-gate field-effect transistors that allow adjusting the potential landscape in semiconducting nanowires/tubes on the nanoscale. To this end, a damascenelike process is employed that allows fabricating a large number of gate structures that are contacted individually and exhibit lengths and inter-gate distances well below 10nm enabling to realize potential landscapes within...
This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an...
Surface roughness causes random shifts in the lowest sub-band level around its ideal position. This gives rise to tail states of an otherwise step-like DOS of the 2D electron gas in the channel. These tail states cause a gradual onset of tunneling in a TFET with vertical tunnel paths and degrade the sub-threshold swing. The impact of roughness of the semiconductor/oxide interface on the transfer characteristics...
Compact modeling has evolved considerably since SPICE was announced to the world in 1973. Many challenging model formulation problems have been solved, and model code itself has changed from being tightly integrated within simulators to being defined in a stand-alone manner. Decades of research led to the former, Verilog-A enabled the widespread adoption of the latter. This paper reviews key steps...
Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of...
Comparison of most mature and promising emerging memory technologies respect to mainstream NAND and DRAM and challenges for the introduction in the market for high density applications.
Ballisticity in 14nm-node FinFETs is investigated by Monte Carlo device simulation. Analytic doping profiles are reverse-engineered to measured transfer characteristics of FinFETs from literature and from this work and good agreement between Monte Carlo simulations and measurements is achieved without any device-parameter calibration. The ballistic ratio, defined as the ratio of the on-current with...
Ferroelectric hafnium oxide (HfO2)attracted a lot of interests since its discovery in 2007. Its scalability and CMOS compatibility are two advantages over conventional ferroelectric materials, favoring new device integration. Doped ferroelectric HfO2 Metal/Insulator/Metal capacitors have been widely studied for DRAM and FeFET applications. Silicon electrodes have not been discussed in much detail...
3D Finite Element ensemble Monte Carlo simulations with integrated 2D Schrödinger Equation quantum corrections are employed to forecast the performance of scaled Si gate-all-around (GAA) nanowire (NW) FETs with unstrained/strained channel. The results from the 3D MC toolbox were compared against experimental I-V characteristics of a 22 nm gate length GAA NW FET with excellent agreement. The NW FET...
Silicon Carbide (SiC) diodes are already commercially available since 15 years and have gained significant market share in power supply and solar converter applications. In the last few years, the SiC device family was enriched by switches. They become increasingly more important for differentiation of power converters in size, weight and/or efficiency. The dedicated material properties of SiC enable...
3D sequential integration requires top FETs processing with a low thermal budget (500°C). The analysis of the origin of the performance difference between Low Temperature (LT) MOSFET and high temperature standard process must take into account a potential EOT modification for short gate lengths. In this work, the difficulty of precise EOT extraction for scaled devices is observed by CV measurements...
Temperature dependent substrate ramp measurements on AlGaN/GaN power high-electron-mobility transistors (HEMTs) are used to extract information on charge redistribution in the buffer structure as a function of substrate bias. The measurements are compared to a theoretical model, representing the ideal capacitive buffer stack. It is found that at room temperature some negative charge is stored in the...
Virtual P-N diodes are emulated in undoped SOI films by biasing the front and back gates such as to induce electrostatically doped regions. The I-V curves are diode-like and can be engineered via gate voltage. We exploit the characteristics of the virtual diode for lifetime characterization, which was considered as a very challenging task in ultrathin SOI films. Two original methods are proposed and...
For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated...
This paper presents a wide-band RF shunt capacitive switch reconfigurable by means of electrically triggered Vanadium Oxide (VO2) phase transition to build a true-time delay (TTD) phase shifter. The concept of VO2-based reconfigurable shunt switch has been explained and experimentally demonstrated by designing, fabricating and characterizing an 819 μm long unit cell. The effect of bias voltage on...
Advanced CMOS nodes target high-performance at lower supply voltage. High-mobility III-V channel materials have the potential to meet this target. Although III-V materials such as InGaAs are beneficial for nFET channels, SiGe (or Ge) provides better hole mobility and is more suited for pFET channels. Therefore, a InGaAs/SiGe hybrid CMOS technology is being pursued for scaled nodes. There are significant...
Here, we report the development of an integrated sensing platform for the field of assisted reproductive technologies (ART), and more specifically for the pre-implantation culture of mammalian embryos and their in situ characterization through evaluation of their metabolic activity. The entire platform consists of a nanoliter-culture chamber, with an integrated oxygen sensor to monitor the respiratory...
SRAM paves the way for new technology nodes as it is more prone to failure due to intrinsic devices variability and technology process. To further boost high density SRAM yield and performance we need assist techniques and increased SRAM bit cell size at the expense of area. This paper discusses SRAM design strategies for future technologies nodes like beyond the N7 node, by comparing higher height...
We present a 5nm logic technology scaling step-up holistic approach for 5-track standard cell design employing electrically gate-all-around nanowire architecture (EGAA NW) with much reduced parasitic capacitance and increased effective width for better short channel control and stronger drive. We suggest SiGe P-channel by Ge Condensation for intrinsic mobility improvement and substrate strain, conformal...
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