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This paper illustrates physical analysis approach to understand the nature of wafer backside metallization (BSM) discoloration and confirmed the problematic process layer with systematic methodology. A series of analyses are carried out in order to determine the cause of BSM discoloration. Our scanning transmission electron microscopy — energy dispersive X-ray spectroscopy (STEM-EDX) lines scan results...
Silver alloy wires with the advantage of low cost, good thermal conductivity and electrical conductivity have been adopted in packaging industry [1, 2]. For plastic encapsulated microelectronics (PEMs) conventional wet decapsulation method is widely used and is implemented by using individual acid or mix acid. However silver alloy dissolves easily in acid. In this study, we present an automatic decapping...
The solder points cracking of a component with package of ceramic ball grid array (CBGA) type is studied in the paper. The cracking cause is found and the failure mechanism is clarified. The weakness of the package structure design is demonstrated by comparing the experiment results of two kinds of components, which provides guidance for the reliable design and application.
SRAM-based FPGA has become a core device in space application. However, based on CMOS technology, SRAM-based FPGA is sensitive for SEU effect. JTAG circuit is a significant module of SRAM-based FPGA, executing boundary-scan test and global configuration function. SEU effect can result in function disturbance of JTAG circuit. To adopt reasonable harden strategies for JTAG circuit, the paper puts forward...
Single Event Effects (SEE) in a stand-alone 1T1R Resistive Random Access Memory (RRAM) are experimentally demonstrated by using pulsed laser irradiation. No bit errors are observed in the RRAM array at an equivalent LET of more than 100 MeV.cm2/mg, indicating that the RRAM memory cells are robust against SEE. The most sensitive regions are the row decoders of the peripheral circuit, with a threshold...
Transmission electron microscopy (TEM) plays an important role in the structural analysis and characterization of materials for failure analysis in integrated circuit industry as device shrinkage continues. It is well known that a high quality TEM sample is the important factor. When the TEM sample was in preparation for cross-section or plane analysis, curtain effect and positioning are the problems...
Demand of short failure analysis has been increasing in semiconductor failure analysis. It is known from the previous studies that many short failure analysis methods are suggested. However, it is extremely difficult to identify the short failure location in recent advanced devices due to the fact of optical resolution limit. On the other hand EBAC has been noted as the high resolution method to identify...
An electrostatic discharge (ESD) protection design by using stacked diodes and silicon-controlled rectifier (SCR) as power clamp is presented to protect a K-band low-noise-amplifier in nanoscale CMOS process. Experimental results show that the proposed design can achieve higher ESD robustness without degrading the radio-frequency (RF) performance. Based on its good performances during ESD stress and...
MM (Machine Model) is an ESD test method used to test for robustness of the device against the ESD event which is induced by the running equipment in fabrication or testing procedure [1]. Due to zero resistance in the equivalent circuit, MM is difficult to simulate. In most cases, MM capability can be calculated from HBM (Human Body Model) result (MM ∼10∼20∗HBM) [2]. But in this study HBM can reach...
Failure analysis is very important in semiconductor business not only for customer satisfaction but also for process improvement and new product development. A successful failure analysis depends mainly on accurate failure verification, appropriate fault isolation techniques, and precise physical analysis steps implemented on the specimen. However, the trend in package development of current ICs makes...
Conductive atomic force microscopy (CAFM) was used to investigate nano-electric performances of semiconductor MOS (metal-oxide-semiconductor) devices. Due to the small tip size (as small as ∼20 nm for PtSi probes), CAFM is capable of imaging both topography and current information of nano-device structures simultaneously with very high lateral resolution. Due to the use of wide ranges of current amplifier...
Time-of-flight Secondary Ion Mass Spectrometry is a well-known surface analysis technique for surface trace level contaminants due to the strength of ultra-high surface sensitivity. However, the mass spectral interpretation for useful information from thousands of elemental and molecular ions is complicated. In this paper, a simpler but effective way for the case study analysis of surface contaminant...
This paper describes the case study of test method of gate source failure and the fault localization approach with aid of device physics theory. The nominal behaviour of IGBT device is turn on the moment gate voltage reaches the threshold voltage. However, in this case the device turn on before the gate voltage reaches to the ideal threshold voltage due to distracted by Gate-source capacitance. On...
In this paper, it is reported for the first time that, in nanoscale high-k/metal-gate MOSFETs, the hot carrier degradation (HCD) follows a two-stage law in some stress conditions. Both interface traps and oxide traps contribute to HCD causing its time-dependence varies with different stress modes. The results are helpful for the physical understanding of HCD in nanoscale devices.
Ion implantation is the most important silicon doping method in the process of semiconductor manufacturing. The common used analysis methodology such as FIB/SEM/TEM is restricted in analyzing the ion implantation related defects, while the chemical stain technology can provide very essential data in ion implantation process. The etching mechanism of silicon is very complicated with the mixture of...
In this study, we establish the SDL (soft defect location) system based on the DALS module of new Hamamatsu Phemos1000 system to analyze the temperature sensitive failure. Our results show that the DALS module is a significant platform to establish the SDL system on because it can mark the defect spot synchronously with the laser scan, and with some external equipment added in, it can isolate the...
Reliability of Superjunction (SJ) MOSFET is closely related to its manufacturing process. Experiments are carried out to investigate the electrical characteristics in high temperature of SJ MOSFET produced by deep trench filling technology. Filling holes are confirmed to be responsible for the performance deterioration in high temperature and the mechanism has been analyzed thoroughly.
The influence of forward current freewheeling time on the reverse recovery di/dt robustness of Superjunction (SJ) MOSFET body diode is investigated in detail. It is found that the maximum di/dt capability of body diode is improved dramatically with reducing the forward current freewheeling time. To explore this phenomenon, physical TCAD simulations and experiments have been carried out. It shows that...
As a key part of failure analysis function in semiconductor foundry industry, TEM micro-topography becomes more and more important while semiconductor devices' critical dimensions get smaller and smaller. And the FIB/TEM sample preparation technique takes the first priority to achieve high quality TEM pictures. Normally FIB operators have to avoid sample defects such as sample bending, poor thickness...
Electro optical techniques including EOFM (Electro Optical Frequency Mapping) and EOP (Electro Optical Probe) are common dynamic optical probing techniques used during failure analysis. This paper demonstrated two real cases to show the application of these techniques on the fault isolation of high resistive vias.
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