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In order to interconnect ultrafine pitch Cu-pillar/Sn-Ag micro bump, Non Conductive Films (NCFs) have been used. During thermo-compression bonding processes, applied pressure and heat make molten solder deform and wet on the sidewall of Cu-pillar. As a result, large Sn-Ag/Cu-pillar sidewall interface reaction makes Sn consumption faster and the Kirkendall void formation. In this study, novel double-layer...
In this paper, the processing and integration challenges addressed during the 3D packaging of a ~400 mm2 logic die are presented and discussed. The logic die was fabricated using GLOBALFOUNDRIES' 14-nm technology with 5x55 µm Through Silicon Vias (TSVs) integrated in the process as a via middle flow [1]. Fully fabricated test wafers were thinned down to 50 µm, using Amkor Technology's Middle End of...
This paper presents the development of Al-Ge eutectic bonding for wafer level chip scale packaging of MEMS sensors. Al is sputtered on the MEMS wafer while an Al/Ti/Ge stack is sputtered on the cap wafer. The bonding temperature and bonding time are 430°C and 30min, respectively. A CMOS compatible Ti/Ni stack was deposited as getter on the cap wafer to maintain the vacuum level inside the cavity....
3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression...
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12...
The reliability of copper through-silicon vias (TSVs) has been shown to be largely determined by the microstructure and extrusion statistics, and the mechanism for this requires further investigation. Synchrotron x-ray microdiffraction is an advantageous technique for TSV measurements due to its high beam intensity, which allows for full stress derivation with submicron resolution, and its nondestructive...
We propose combined solder-TSVs and microbumpsfor cost reduction of 3-D integration. Conventional via-last TSV technology requires microbump formation. We eliminate the microbump process for low cost 3-D process. In our process, TSVs and microbumps are formed simultaneously with solder. We demonstrate this process by fabricating daisy chain chips with 20-µm-pitch TSVs. The TSVs are 7-µm diameter,...
In this study, we report the reduction of via extrusion for Cu through-silicon vias (TSVs) through the application of a metallic cap layer. The basic idea of this approach is based on suppressing the mass transport which causes via extrusion on the top surface of TSVs. Two materials, W and Co, were deposited as the cap materials. Experiments were carried out to characterize the extrusion behavior...
This paper demonstrates the feasibility of 3D embedded capacitor for on-chip applications in 3D/2.5D ICs. Compared with stand-alone trench capacitor, its capacitance density is 2.5 times higher. 3D embedded capacitor can be implemented by embedding MIM capacitor into TSV trench to minimize occupied area. In this study, structure integrity of test vehicles was firstly examined with SEM, under which...
This paper applies for the first time an RF equivalent of the four-point probe Kelvin DC technique to characterize the TSV inductance. This RF approach is based on two-port S-parameter measurements over a wide frequency range using a vector network analyzer (VNA). The approach is easy to implement to determine the TSV inductance, which can be complementary to the DC Kelvin measurements. In addition,...
A model of copper and carbon nanotube (CNT) composite filled through silicon via (TSV) is developed to estimate signal delay of a novel interconnect, employed in 3D integrated circuit (IC) design. The main objective of 3D interconnect is to electrically connect two stacks of circuits and offer robust chip functionalities. The 3D integration scheme allows independent design of operational blocks in...
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