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Silicon interposers are frequently used in memory and network processor systems to closely integrate multiple chips and improve the performance of high-speed systems. The proximity provided by silicon interposer greatly improves bandwidth, power, and latency by simplifying communication and clocking of the links. However, the design of silicon interposer systems poses new challenges in managing the...
In this paper, the processing and integration challenges addressed during the 3D packaging of a ~400 mm2 logic die are presented and discussed. The logic die was fabricated using GLOBALFOUNDRIES' 14-nm technology with 5x55 µm Through Silicon Vias (TSVs) integrated in the process as a via middle flow [1]. Fully fabricated test wafers were thinned down to 50 µm, using Amkor Technology's Middle End of...
Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active...
3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression...
Smaller footprint, thinner packages and simultaneously increased functionality are general requests for all electronic products and as well hold true for MEMS sensors. Current standard packaging technology for MEMS sensors is stacking the ASIC and MEMS silicon dies on a substrate. The sensitive dies are then either protected by over-molding or by attaching some sort of lid. Typical substrate materials...
A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye...
In this work, the development of engineered silicon substrates for a novel via-middle TSV integration concept is demonstrated. These substrates include 3D buried etch-stop layers which provide both an ideal vertical and lateral etch-stop for TSV trench etching thus enabling the simultaneous realization of different size of TSVs on the same silicon substrate. Beside standard BiCMOS and TSV fabrication...
10um × 100um TSV was prepared by deep reactive ion etching process. Barrier and seed layer were deposited by physical vapor deposition process and prior to Cu electroplating, Ni was electroplated on seed layer. Cu electroplating was optimized for solid TSV filling. To remove excessive Cu on field area, chemical mechanical polishing process is used in conventional TSV fabrication process. In this study,...
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12...
This paper reports two types of in-house fabricated aluminium nitride (AlN) based piezoelectric resonators, namely the thickness mode resonator and the Lamb-wave mode resonator, which are capable to be integrated with Through Silicon Via (TSV) technology, forming the basis of advanced filters, duplexers and multiplexers. Both types of the resonators, which are fabricated using a CMOS compatible platform,...
High thermo-mechanical stresses are usually induced in through silicon via (TSV) structures due to the mismatch of coefficients of thermal expansion (CTE) between copper and silicon in Cu filled TSVs, which has brought an increasing concern for the reliability problems during fabrication process and operation of electronic devices. The size, shape and orientation of Cu grains in TSVs and their effects...
Traditional IC packaging requires chips to be assembled at the same level, while recently thrived 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similarfootprint, and this approach not only can reduce overall package size, but also can improve electrical interconnection performance. The primary difference between 2.5D/3D IC lies in...
The reliability of copper through-silicon vias (TSVs) has been shown to be largely determined by the microstructure and extrusion statistics, and the mechanism for this requires further investigation. Synchrotron x-ray microdiffraction is an advantageous technique for TSV measurements due to its high beam intensity, which allows for full stress derivation with submicron resolution, and its nondestructive...
We propose combined solder-TSVs and microbumpsfor cost reduction of 3-D integration. Conventional via-last TSV technology requires microbump formation. We eliminate the microbump process for low cost 3-D process. In our process, TSVs and microbumps are formed simultaneously with solder. We demonstrate this process by fabricating daisy chain chips with 20-µm-pitch TSVs. The TSVs are 7-µm diameter,...
Via-Last (VL) Through Silicon Via (TSV) is being pursued for its added benefits of process flow simplicity, lower cost and integration flexibility. A novel, CMP-less VL TSV integration flow has been reported previously. Based on cost model analysis, ~9% TSV cost reduction can be achieved by elimination of the Cu Chemical Mechanical Polishing (CMP) process. In addition, it enables applications that...
Today, applications like data center/cloud, mobility and Internet of Things (IoT) are key market drivers for semiconductor industry. To meet the requirements of next generation Information and Communication Technology (ICT) systems, the packaging technology has to evolve along with the Integrated Circuit (IC) technology scaling. At the same time, design and development of packages have to meet the...
In this study, we report the reduction of via extrusion for Cu through-silicon vias (TSVs) through the application of a metallic cap layer. The basic idea of this approach is based on suppressing the mass transport which causes via extrusion on the top surface of TSVs. Two materials, W and Co, were deposited as the cap materials. Experiments were carried out to characterize the extrusion behavior...
The motivation behind this study is to detect barrier and dielectric liner degradation in a copper (Cu) through-silicon via (TSV) structure. The integrity of titanium (Ti) barrier and silicon dioxide (SiO2) dielectric liner are evaluated via a non-destructive electrical characterization method after being subjected to different stress tests such as high temperature storage (HTS), temperature cycling...
Electromagnetic (EM) and circuit modeling are the prevailing practices for the anticipation and extraction of data transfer performances of 3D interconnects in a system-in-package (SiP). In comparison, this paper proposes a more abstract and cost-efficient evaluation method and an enhancement method thereof from the perspective of network information theory and communication channel modeling. Firstly,...
This paper demonstrates the feasibility of 3D embedded capacitor for on-chip applications in 3D/2.5D ICs. Compared with stand-alone trench capacitor, its capacitance density is 2.5 times higher. 3D embedded capacitor can be implemented by embedding MIM capacitor into TSV trench to minimize occupied area. In this study, structure integrity of test vehicles was firstly examined with SEM, under which...
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