The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Colloidal quantum dots (QDs) applied in illuminants and displays have been offered great prospects due to their narrow and tunable emission bands. However, the QD's incompatibility to encapsulant and sensitivities to oxygen and moisture are still limiting their performance in white light emitting diode (WLED). In this research, we have developed a new kind of QDs composites as QDs luminescent microspheres...
High power consumption & high input/out (IO) density are requested by modem electronic components such as high-density electronics, communication satellites, advanced aircraft, networking server and telecommunication devices. Challenges in the heat dissipation of an electronic package arise from the continued increase in power dissipation and power density of higher-power devices. A thermal interface...
In this paper, the processing and integration challenges addressed during the 3D packaging of a ~400 mm2 logic die are presented and discussed. The logic die was fabricated using GLOBALFOUNDRIES' 14-nm technology with 5x55 µm Through Silicon Vias (TSVs) integrated in the process as a via middle flow [1]. Fully fabricated test wafers were thinned down to 50 µm, using Amkor Technology's Middle End of...
Heavy corrosion on Aluminum (Al) bond pad, with a "mud-crack" appearance, in a Copper (Cu) wire-bonded assembly can be a critical failure mode, especially under harsh conditions such as in automotive environments. Such corrosion can be associated with the presence of contaminants such as chloride ions (Cl-). However, the exact corrosion activation mechanism remains unclear and hence the...
Electroplating is a low cost process where metal ionsin a solution are reduced by an applied electric field onto aconductive substrate. This process has been studied extensively, but is still critical for modern technology and R&D. In the HPinkjet printing business, electroplating is primarily used in themanufacturing the orifice plate (OP) for integrated print-headproducts. To extend the OP functionality,...
Fan-Out Wafer Level Packaging (FOWLP) is one of the latest trends in microelectronics packaging. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, low thermal resistance, high RF performance due to shorter interconnects together, as the direct IC connection by thin film metallization...
In this study, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, carrier material and thickness, and die-attach film, on the warpage after post mold cure (PMC) and...
The tremendous growth in smartphones and tablets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of integrated circuit (IC) devices, resulting in the need for more advanced and sophisticated packaging techniques. In particular, the integration of the application processor...
Today, Fan-out wafer level packaging (FO-WLP) is considered to be the key advanced packaging platform to meet the technological and cost roadmap requirements of the industry. The Backbone of this technology is the reconstitution of an artificial wafer or substrate with known good dies. This characteristic is an enabler to develop much larger substrate sizes beyond 300mm to take advantage of economies...
Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key...
This analysis focuses on two of the primary variations of fan-out wafer level packaging: die-first packaging in which the die are placed face down, and die-last packaging. These two technologies share many of the same activities, but those activities occur in a different order. One key factor setting these two process flows apart is yield. Even with the assumption that the same level of defects are...
With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to fan-in...
The current automotive market for the integrated circuit (IC) packaging industry has grown significantly due to the increasing need for automation and higher performance in vehicles. These changes in the automotive market will enable cars to be more reliable and intelligent. To address the increasingly complex demands of the automotive market, the semiconductor packaging industry is shifting its focus...
In this paper, a fully BiCMOS integrated microfluidic technology platform for Lab-on Chip (LoC) applications is presented. Fusion bonding and adhesive bonding techniques are applied to realize a 3-wafer-stack integration. A glass wafer is used on top of the BiCMOS wafer and the Si channel wafer to enable simultaneous optical and electrical measurements. An alignment accuracy of less than 1 µm between...
Traditional IC packaging requires chips to be assembled at the same level, while recently thrived 2.5D/3D IC packaging utilizes skyscraper approach to stack various types of chips with diverse functions occupying similarfootprint, and this approach not only can reduce overall package size, but also can improve electrical interconnection performance. The primary difference between 2.5D/3D IC lies in...
Wafer Level Package (WLP) is a packaging technology focusing on IC packaging at wafer level instead of chip level. Conventional WLPs are designed for fan-in chip scale packaging but the shrinkage of pad pitch and size at the chip to package interface is much faster than the shrinkage at the package to board interface. Fan-Out Wafer Level Package (FO-WLP) is key technology to solve this problem. FO-WLP...
Fan-Out Wafer Level Packaging (FOWLP) has recently seen a tremendous growth in a broad span of application in telecommunications, automotive and other markets. Its versatility allows its continuous development to accommodate more and more types of components. In light of expanding the technology to include new family of sensors such as MEMS/NEMS, Bio-chips with Microfluidics, magneto-resistive devices...
Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect...
To take full advantage of silicon carbide (SiC) devices' superior electrical and thermal performance, advanced power module packaging designs and suitable materials are required. In this paper, the development of a new high power density module using the Power Overlay (POL) packaging platform is presented. The wirebond-less packaging platform has shown significantly reduced electrical parasitics,...
Today, applications like data center/cloud, mobility and Internet of Things (IoT) are key market drivers for semiconductor industry. To meet the requirements of next generation Information and Communication Technology (ICT) systems, the packaging technology has to evolve along with the Integrated Circuit (IC) technology scaling. At the same time, design and development of packages have to meet the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.