The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In order to interconnect ultrafine pitch Cu-pillar/Sn-Ag micro bump, Non Conductive Films (NCFs) have been used. During thermo-compression bonding processes, applied pressure and heat make molten solder deform and wet on the sidewall of Cu-pillar. As a result, large Sn-Ag/Cu-pillar sidewall interface reaction makes Sn consumption faster and the Kirkendall void formation. In this study, novel double-layer...
Isotropic conductive adhesives (ICAs) based on metal-coated polymer spheres (MPS) have shown high potential for low-temperature, high-throughput assembly of a transducer array on a substrate in ultrasound imaging applications. The process of bonding and subsequently dicing a transducer stack on a flexible substrate was evaluated. The bonding material was MPS-based ICAs containing a commercial epoxy...
The advancing heterogeneous integration of various electronic components into a single package requires in particular further development of bonding technologies towards lower temperatures. In our present study, we show the successful joining of dies consisting of Cu-microbumps with In solder caps. Stable interconnections were achieved at a bonding temperature of 180 °C in 2 min by solid-liquid-interdiffusion...
A novel method of fabricating high transmittance and broadband terahertz (THz) polarizers is introduced with several advantages. A polarizer with an approximate 100% transmittance is demonstrated with single central frequency of anti-reflection (AR) layers between 0.5 THz and 2 THz. Broadband polarizer, which has a transmission spectrum of over 70% uniformity, is fabricated by bonding two wafers with...
For improvement of the productivity and the cost reduction, FOWLP (fan-out wafer level package) or FOPLP (fan-out panel level package) process using large-sized substrate has been actively developed in recent years. Above all, we will report about the novel TCB (thermal compression bonding) equipment which is even applicable to a 3D-IC stacking process and a fine pitch FOWLP or FOPLP of RDL-first...
Dynamic changes in distribution of mechanical strain generated during wire bonding in Si under and near the bonding pad were measured by using a piezoresistive linear array sensor. The sensor was designed to be able to determine strains in the directions normal and parallel to the surface. Bonding dynamics of Cu and Au balls were investigated. We can clearly observe the oscillating strain according...
Soft soldering is still the standard bonding method in order to provide a large void-free joining area in power electronics module applications. Ag sintering has been proven for small-area die attach applications to increase junction temperature and reliability. In this paper, we explore silver sintering technology further for large-area high-temperature substrate bonding in order to enable full benefits...
This study investigated the relations between base resins and flux compounds applied to NCF (Non Conductive film) for thermal compression bonding with micro Cu pillar bumps. As the use of NCF expands, outgas during flip-chip bonding process is being recognized as a serious problem because it lowers both of the productivity and the package quality. The flux compounds which are normally used to get...
To improve the latency and bandwidth performance for future high performance computing application, a sub-micron electrical interconnection composed of metal capping layer with sub-micron thickness on typical copper CMP (chemical mechanical polish) BEOL (back-end of line) structure is demonstrated, and the corresponding metal deposition including Ni, Pd, Au using electro-less technique are reported...
Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die...
The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure ( 20 MPa. The combined reduction of dielet interconnect pitch, dielet-to-dielet spacing and trace pitch will enable a Moore's law for packaging.
Drop test reliability of the 20 mm × 20 mm RDL-first FOWLP on bottom and 8 mm × 8 mm WLCSP on top for Package on Package (PoP) test vehicle was validated by the experimental testing in this paper. The results show that the built up PoP test vehicle can pass 30 times of drop impact test and some samples can pass 200 times drop impact test with the loading of 1500 G/0.5 ms. The failure mechanisms of...
In this paper, we demonstrate a low temperature, low pressure wafer level damascene compatible Cu-Cu thermocompression bonding using an optimized ultra-thin Copper-Nickel-Manganese based alloy layer, Manganin as passivation layer. Surface oxidation and roughness are the major bottlenecks in achieving low temperature and low pressure high quality Cu-Cu bonding. Manganin alloy have dual role of protecting...
In this paper, a novel method of Cu-Cu bonding by using the Cu nanosolder paste was proposed. The pure Cu nanoparticles used for preparing the Cu nanosolder paste were synthesized with simple routes and relatively high yields. The Cu nanoparticles were homogeneously dispersed with an average size around 60 nm. The sintering and bonding performance of Cu nanosolder paste were investigated, while an...
This paper presents the development of Al-Ge eutectic bonding for wafer level chip scale packaging of MEMS sensors. Al is sputtered on the MEMS wafer while an Al/Ti/Ge stack is sputtered on the cap wafer. The bonding temperature and bonding time are 430°C and 30min, respectively. A CMOS compatible Ti/Ni stack was deposited as getter on the cap wafer to maintain the vacuum level inside the cavity....
"Molded reflow process" which is novel high productive 3D stacking process has been developed. The process is a serial process of the first step of chip pre-bonding on the wafer, the second step of resin over-molding and the third step of connection by reflow furnace. Molded reflow process provided not only high productivity compared with thermal compression bonding process but also excellent...
Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D IC's. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes...
High-performance computing has been aggressively driving pitch and performance requirements for off-chip interconnections over the last several decades, pushing solder-based interconnections to their limits. The most leading-edge Cu pillar technology faces many fundamental challenges in scaling to pitches below 30um, in particular with stress management and increased risks of Au embrittlement as solder...
Recently, silver solid solution phase with indium, (Ag)-xxIn, has been demonstrated to be one of potential candidates of metallic packaging material for future high-power electronics bonding and interconnection applications due to its great anti-tarnishing property and superior mechanical properties, such as high ductility and high ultimate tensile strength. To further explore and utilize its great...
3D multi-layer chip stacking is a significant assembly challenge with dependencies on die size and thickness, interconnect pitch, bump diameter, number of dies involved, and die warpage. The assembly processes used to overcome the technical difficulties associated with the stacking of medium and large logic dies with fine pitch copper pillar bumps is discussed, including mass reflow and thermo-compression...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.