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New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier...
The impact of polysilicon thickness (THK-poly) and channel hole diameter (CHCD) on channel boosting potential during program inhibit has been studied with Sentaurus device simulator for three dimensional (3D) NAND memory. According to the distribution of boosting potential along the channel, the potential level of thinner THK-poly is higher than that of thicker one. Moreover, the correlation between...
The TSV(Through-Silicon Via) plays an important role of inter-layer interconnection in 3D ICs. However, TSV is defect prone. This paper proposes a new scheme based on oscillator to monitor the defects of TSV at the prebond stage.
The emerging applications is the dominant factor that drives the evolvement of computer technologies and architectures. Among the emerging applications these days, neural networks are the most attention-grabbing one. To unleash the benefits of neural network, the architecture optimization is a necessity. In this paper, the architecture requirements of neural network is first reviewed. Then based on...
Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL in 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select transistor leakage suppression is essential in 3D NAND Flash Memory, in consideration of boosting potential and program disturbance. Compared to single Si drain select transistor in 2D planner Flash Memory,...
To facilitate the development of low-cost, low-power, and high-density hardware neural networks, we have successfully developed a Ta/TaOx/TiO2/Ti RRAM-based synaptic device. The device exhibits numerous synaptic functions resembling those in biological synapses, including synaptic plasticity of potentiation and depression, spike-timing dependent plasticity, paired-pulse facilitation and a transition...
This paper describes selected technologies for the 3D integration of MEMS devices. This comprises a Via Last approach for the formation of MEMS TSVs and a Cu based thermo-compression bonding method for the realization of small 3D-WLP devices. Moreover, the Aerosol Jet technique is discussed as method for the final assembly by means of printing conducting lines over 3D topography.
The concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control. This approach is especially important for the epitaxial deposition of very thin (nm) layers. Here, the existences of Ge oxide in the CVD reactor resulting from former Ge deposition and hydrogen termination of the wafer surface is impacting the epitaxial growth essentially...
This paper presents the design, fabrication, and testing of a novel 3D-printed triboelectric generator. By adopting the saw-toothed button structure, the friction surface at the interface is enlarged and enclosed, which helps to increase power generation capability and shrink device volume. The major parts of the proposed device is fabricated through 3D-printing, and the entire device is assembled...
Fast machine learning is required for future real-time data analytics. This paper introduces a 3D multi-layer CMOS-RRAM accelerator for learning on neural network. Given input of buffered data hold on the layer of a RRAM memory, intensive matrix-vector multiplication can be firstly accelerated on the layer of a digitized RRAM-crossbar. The remaining algorithmic operations such as feature extraction...
We have developed a novel single-gate vertical channel (SGVC) 3D NAND Flash architecture. The device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. The ultra-thin body TFT device enables tight initial Vt distribution as well as excellent short-channel effect that is comparable to and sometimes superior than the more prevailing gate-all-around (GAA) macaroni devices...
A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistor's Vth distribution by adopting under-channel implant in this work.
In this paper, the widely adopted “hole in the inversion layer” (HIL) model for predicting the amplitude of random telegraph noise (RTN) in nanoscale MOSFETs, is theoretically revisited with focusing on its scaling limit and validation range. It is found that this simple physical model fail to apply on ultra-scaled devices with L<20nm and/or W<10nm, due to the non-negligible impact from source/drain...
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