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Ultra-thick and ultra-thin Silicon PIN detectors are specially applied in high particles detections. The corresponding leakage current is investigated. The ultra-thick and ultra-thin gated diodes structures based on high resistivity silicon substrates are fabricated and tested to analyses the reverse leakage current for silicon PIN detectors application. It is concluded that the contribution of the...
A SiC Schottky barrier diode (SBD) with a novel junction termination structure including two mesas and one P+ guard ring was proposed and demonstrated. Under reverse bias, charge will be attracted to the position of guard ring instead of concentrating at the edge of Schottky junction due to the existence of the first mesa. In addition, the second mesa will further cause the high electronic field expanding...
A novel temperature analysis method for compound semiconductor integrated circuits based on iteration algorithm has been presented. The iteration algorithm has been developed with efficient numerical calculation in MATLAB. This method has been applied to a simple module including 9 devices and the calculated temperature distribution has been compared to the simulated result by 3D simulation tool....
The shallow junction is used in the PDSOI technology. Unfortunately, the standard diode model maybe not suit to this PN junction. A simulation model is proposed based on the PDSOI process. The additional influence of the voltage bias of the junction to the capacitance is considered in this model and then the model is well verified by the measured data.
A comparative investigation of γ-ray total dose ionization damage at high and low-level injection (HLI/LLI) for different dose rate irradiation in double polysilicon self-aligned bipolar NPN transistors is presented. The transistors reveal anomalous dose rate radiation responses for Emitter-Base (E-B) electrical field strength in forward active mode. This effect is probably associated with the different...
Designing and fabrication of 4kV, 20A 4H-SiC PiN diodes with JTE junction termination structure have been investigated in this paper. A bevel mesa structure and a single-zone junction termination extension (JTE) have been employed to achieve the target voltage. Finally, an optimized mesa structure without sub-trench (mesa height of 2.2 µm and mesa angle of 20°) has been experimentally demonstrated...
We present a novel design of bulk transmit-receive (T/R) switch FET to reduce switch loss and harmonics. Along with this we present an improved low-noise amplifier (LNA) bipolar design in a 350nm SiGe BiCMOS technology for providing better WiFi RX path performance in 802.11ac wave-2 applications. Tighter lithography aspects of 180nm is utilized to make these critical performance advancements.
A novel high-voltage trench SOI LDMOS with ultra-low specific on-resistance (Ron,sp) is proposed and it features a Trench-Field-Enhanced (TFE) structure around the deep trench dielectric layer. The TFE structure consists of an L-shaped p-region, a symmetrical-L-shaped n-region and two high-doping p+ regions. In the OFF state, as the trench-field-enhanced effect (TFE-E), electric field in the bulk...
In this paper, a novel triple reduced surface field (RESURF) LDMOS with N-top layer based on substrate termination technology (STT) is proposed. The analytical models of surface potential, surface electric field, breakdown voltage (BV) and optimal integrated charge of N-top layer (Qntop) for the novel triple RESURF LDMOS are achieved. Furthermore, STT is applied to avoid the premature avalanche breakdown...
Degradation of n-type low temperature poly-Si (LTPS) TFTs is investigated under bipolar gate pulses with a small drain bias. It is found that degradation behaviors are similar to those caused by the bipolar gate pulses with source and drain grounded. Dynamic hot carrier (HC) degradation is the dominant mechanism. However, device degradation also strongly depends on the drain bias. Four-terminal poly-Si...
This paper investigates the reliability of junctionless MOSFETs based inverter by 3D TCAD simulation. The results show the I–V behavior of junctionless SOI-MOSFETs is highly resistant to accumulated fixed charge in oxide. Then the performance of junctionless device-based inverter is discussed. VM of juncitonless device-based inverter maintains within 0.05V and the transient response time shows very...
Experiments are carried out to investigate the relationship between the robustness of super junction VDMOS (hereafter SJ-VDMOS) and its body diode characteristics. It is found that the voltage overshoot is responsible for the device failure. The mechanism of voltage overshoot has been analyzed thoroughly and some measures to smooth the overshoot are provided. The improved 600V SJ-VDMOS shows a higher...
A possible strategy for the characterization of grown-in and processing-induced electrically active point and extended defects in high-mobility substrates is presented and illustrated by examples obtained on Ge as a prototype system.
The ultra-shallow NiGe/p+-Ge/n-Ge Schottky junctions with dopant segregation have been fabricated using Indium spin-on dopant and thermal diffusion, followed by NiGe growth with microwave annealing technique. The total junction depth of the NiGe/p+-Ge/n-Ge Schottky junction was scaled down to 9 nm, containing 6-nm-thick NiGe and 3-nm-thick p+-Ge region. It is found that the junction leakage current...
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