The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and...
An improved power-rail electrostatic discharge (ESD) clamp circuit is presented in this paper. The proposed circuit maintains a much lower leakage current over the static-triggered circuit while the false-triggering immunity of the design is fairly superior to the traditional transient-triggered circuit. Besides, by utilizing the feedback technique and capacitance-boosting technique, the area occupied...
A new reliable Electrostatic Discharge (ESD) power-rail clamp circuit has been proposed in this paper. The new circuit structure has achieved good results in reducing leakage current, anti-false triggering, increasing discharge transistor's turn on time. During the ESD event, the proposed circuit has a discharge time of 755.22ns, which is about 6.74 times that of conventional R-C power-rail clamp...
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
On-chip electrostatic discharge (ESD) protection are required for all ICs. Unfortunately, ESD-induced parasitic capacitance (CESD) will seriously affect performance of high-speed and RF ICs. Careful design balance of ESD protection level and minimizing ESD-induced circuit performance degradation has become a major design challenge for high-speed and RF ICs. This paper presents a comprehensive study...
Electrostatic discharge (ESD) effect in the p-type polycrystalline thin film transistor (poly-Si TFT) are investigated by employing a transmission line pulses with different durations (100ns and 200ns). The experimental results shown that P+/poly-Si junction governs the transition of the off-state phase and on-state phase observed in the TLP I–V curves. In addition, the breakdown mechanism in the...
an area efficient clamp is presented and validated in 65nm low leakage CMOS process. With this novel design, only a very short time constant RC timer is required for triggering and keeping the clamp turning on for shunting the ESD current. And the leakage is greatly reduced in normal operation because of the small capacitor. Robust ESD protection capability and no risk of power on mis-triggering problems...
The analysis of self-heating effect in a SOI LDMOS device under an ESD stress is presented in this paper. TCAD tools are used as the platform to explore the physical process of the bulk LDMOS device and the influence of buried oxide layer inserted in the substrate. Simulation results uncover that the buried oxide layer degrades the current-handling ability and changes the lattice temperature distribution...
A robust ESD device for 5V circuit protection was designed and fabricated in a 0.5-µm 5V CDMOS process. It is composed of multi-fingered GCNMOS and ballasting-resistor. The ESD performance of such device with strip layout style is investigated by employing transmission line pulse (TLP) measurement. A double-triggered phenomenon is detected in the multi-fingered GCNMOS with ballasting-resistor. And...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.