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A fully integrated, reconfigurable step-up DC-DC switched-capacitor power supply solution for energy harvesting system is presented in this paper. A new series-parallel architecture of step-up switched-capacitor converter with Pulse Skip Modulation (PSM) is proposed. This converter generates a stable regulated output (1.2V) from an ultra-low input voltage of 0.3V–1.2V. The designed converter achieves...
A wideband capacitor cross-coupled common-gate low-noise amplifier (CGLNA) featured with improved linearity is proposed. The linearity is enhanced by complementary multi-gated transistor (CMGTR) technique. The bulk voltage and scaling size are tuned to shift the nonlinear coefficients of auxiliary transistors, compensating the nonlinearity of main transistors. Simulated in a 0.18 µm RF CMOS process,...
In order to mitigate the electric field crowdingingate dielectrics and solve the reliability issue, high dielectric constant (κ) materials such as Al2O3 was applied in SiC metal-oxide-semiconductor (MOS) capacitors. High quality thin film Al2O3 was deposited on 4H-SiC by thermal atomic layer deposition (ALD), followed by post deposition annealing (PDA). The PDA was conducted in oxygen atmosphere at...
A new reliable Electrostatic Discharge (ESD) power-rail clamp circuit has been proposed in this paper. The new circuit structure has achieved good results in reducing leakage current, anti-false triggering, increasing discharge transistor's turn on time. During the ESD event, the proposed circuit has a discharge time of 755.22ns, which is about 6.74 times that of conventional R-C power-rail clamp...
A comprehensive behavioral model of Track-and-Hold Amplifier (THA) based on GaAs HBT, implemented in MATLAB-SIMULINK platform, is presented in this paper. The main error sources of the holding capacitor and non-linear on-resistance are investigated, and the relative non-idealities are modeled. With the behavioral model, SIMULINK simulations were performed to analyze the non-ideal error sources and...
This paper describes a complete process/design co-optimization methodology based on Fully Depleted SOI (FDSOI) technology. A process optimization is detailed through significant effective capacitance reduction, in order to optimize jointly frequency/leakage ratio and high frequency performances. In this objective, an efficient and low cost offset-spacers morphology has been designed to achieve maximum...
A wideband and high linearity IF programmable gain amplifier (PGA) is presented for 60GHz wireless receivers. The core of the circuit is a differential amplifier based on the “flipped voltage follower” (FVF) cell. The FVF cell introduces an additional zero and extends the bandwidth without extra power consumption. The presented PGA has been implemented in 65nm CMOS, and the simulation results show...
In this paper, a novel capacitor self-calibration technique is presented, which can be used in high resolution ADCs, such as SAR ADC and pipeline ADC. The capacitors achieve self-calibration through the adjusting capacitors array and successive approximation (SAR) logic. A 14-bit SAR ADC using capacitor self-calibration technique we proposed has been designed. The simulation result shows that the...
In traditional pipelined ADCs, errors originated by capacitance mismatch, finite amplifier gain, incomplete settling and offset. To overcome capacitance mismatch for >=2.5-bit/stage MDAC architecture, a new background digital calibration strategy is proposed in this paper. Based on this technique, a 14-bit, 40MS/s pipelined ADC is implemented. The simulation results show that ENOB is improved from...
The pre-bond through silicon via (TSV) probing tests and fault localization are important for yield assurance in 3D-SICs. This paper proposes an optimization algorithm to generate the preferable set of test sessions for pre-bond TSV probing tests. Test sessions generated by the optimization algorithm can not only get localization of faulty TSVs in TSV network, but also reduce test time and cost of...
For low cost and high integration, an on-chip compensator implemented in a Buck converter with minimized external pins and high performance is proposed. Trans-conductance amplifiers with constant Gm and high linearity are developed to substitute the resistors; meanwhile capacitance multipliers consisting of high-gain amplifiers are designed to replace the capacitors. Thus, all passive devices in compensator...
A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector (ZCD) is adopted to make the converter work in discontinuous conduction mode (DCM). Due to hysteretic control extremely simplified the control...
This paper presents a power-efficient 100-MS/s, 10-bit asynchronous successive approximation register (SAR) ADC. It includes an on-chip reference buffer and the total power dissipation is 6.8 mW. To achieve high performance with high power-efficiency in the proposed ADC, bootstrapped switch, redundancy, set-and-down switching approach, dynamic comparator and dynamic logic techniques are employed....
With a significant input-to-output conversion ratio from 12V to 1V, single-stage DC-DC conversion solution has obvious benefits on efficiency and cost, compared to the cascaded counterparts, but is generally difficult to control and thus suffers from large regulation inaccuracy. To mitigate these issues, this paper presents a single-stage, adaptive on-time (AOT) hysteretic controlled converter. In...
This paper presents a configurable 1/2/3 order Butterworth low pass(LP)/complex bandpass (CBP) filter for sub-GHz Applications in a 180-nm CMOS process. The filter employs operational transconductance amplifier (OTA) unit with feedforward capacitor instead of conventional two-stage amplifiers to broaden bandwidth while consuming no extra power. In order to achieve a good noise figure, extra noise...
A low phase noise voltage-controlled oscillator for mm-wave applications is presented. The oscillator uses switched-capacitor technique to increase the tuning range. The measured results show that the oscillator achieves a phase noise of −100dBc/Hz at 1MHz offset from the carrier frequency of 49.7GHz, while consuming 5.5mA current from a 0.9V supply. A wide tuning range percentage of 12%, i.e. 43...
an area efficient clamp is presented and validated in 65nm low leakage CMOS process. With this novel design, only a very short time constant RC timer is required for triggering and keeping the clamp turning on for shunting the ESD current. And the leakage is greatly reduced in normal operation because of the small capacitor. Robust ESD protection capability and no risk of power on mis-triggering problems...
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