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High-Bandwidth Digital Content Protection(HDCP)-it is a technology method which is used to protect the high definition signs. This paper focuses on design and verification of authentication part, the most important of a HDCP2.2 transmitter. Besides architectural analysis and design approach discussions, a detailed micro architecture, including signature verification, key encryption and revocation...
This paper presents a conjugate gradient algorithm of convergence speed and accuracy in pipelined ADCs. The pipeline ADC error acts as the objective function of the method. The objective function gradient gradually produce conjugate direction which acts as the search direction to obtain the minimum point, where, the search direction is just a combination of the negative gradient direction with the...
This paper has researched the theory and design principle of GF (28) multiplication which is widely applied in symmetric cryptograms. With the principles in mind, three kinds of reconfigurable multipliers based on x time, xm modular and product separately have been implemented and their merits and demerits also have been investigated. Having analyzed the mix-column and reverse mix-column transformation,...
A novel temperature analysis method for compound semiconductor integrated circuits based on iteration algorithm has been presented. The iteration algorithm has been developed with efficient numerical calculation in MATLAB. This method has been applied to a simple module including 9 devices and the calculated temperature distribution has been compared to the simulated result by 3D simulation tool....
Coarse-grained reconfigurable block encryption array (REBA) provides massively parallel computing resources but traditional mapping scheme does not develop the advantages of REBA. In this paper, aiming to improve the performance and resource efficiency of algorithm mapping, we research the structure of familiar block cipher algorithm, and propose the speed-up model based on loop unrolling and the...
Motivated by reduction of computational complexity, this work develops a pipelined adaptive filter architecture using the sign-error least mean square (SELMS) algorithm. The proposed algorithm was implemented with less than half the amount of calculation consumed for the conventional architectures. Besides, the proposed designs derived by retiming technique and with low latency also provide a faster...
Linear amplification with nonlinear components (LINC) is an attractive technique to achieve linearity amplification with high efficiency. The linearity and resolution of the delay line play a great important role for the performance of LINC transmitters. In order to overcome the limitation of linearity and resolution, a delay-based all-digital phase modulator with calibration algorithm is proposed...
A novel calibration algorithm called Dynamic Mismatch Compensation is proposed to reduce amplitude, delay and duty-cycle errors of MSB current cells (MSBs) in current-steering DACs. The DMC algorithm, suitable for high resolution and high speed DAC applications, can improve the SFDR by more than 10dBc, according to the behavioral-level DAC simulation results in Matlab. Transistor-level simulation...
Low power design is critical in today's chip design. Clock tree takes much of chip power. “Clock tree cost” is introduced to help design low power clock tree. Five methods are proposed to reduce “clock tree cost” and improve clock tree efficiency. They include clock sink depth check, redundant scan mux check, redundant clock gating cell check, CCOPT (Clock Concurrent Optimization) and simple clock...
We present an efficient layout decomposition flow and the corresponding optimization algorithms to minimize the stitches for double patterning lithography. Also the given power/ground preprocessing method for the flow reduces the complexity, and improves the speed and quality to the layout decomposition. Experiments show that our algorithms can effectively get the better results compared with other...
Network-on-chip (NoC) emerged as a promising alternative to the bus and point-to-point communication architectures. Recently 3D NoC become a hot topic. While complex 3D NoCs will generate a large amount of data to deal with, NoCs suffer from intermittent congestions and link overflows, especially when the network bandwidth is limited by the area and energy budget. In this paper, we explore a technique...
An analog MPPT controller suitable for DMPPT solar array is presented in this paper. In order to achieve an accurate tracking, “Perturb and Observe” tracking algorithm is applied. PWM+ burst dual mode control strategy is adopted in the controller to obtain a high efficiency in both high and low irradiation intensity. Finally, simulation results and experimental results are reported and discussed....
To realize the high-speed performance of the processor, we need to research an efficient and flexible interconnection structure. In this paper, we propose a multistage interconnect structure based on Crossbar in the Coarse-Grained Reconfigurable Logic Array (CGRLA). Inner internet implements the connection of Functional operation unit flexibly and the outer internet implements the data transmission...
In this paper, a high-flexibility and energy-efficient reconfigurable symmetric cryptographic processor architecture is presented, which is based on very-long instruction word (VLIW) structure. By analyzing basic operations and storage characteristics of symmetric ciphers, the application-specific instruction-set system for symmetric ciphers is proposed. Eleven kinds of reconfigurable cryptographic...
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