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We report a comprehensive etching study on the gate recess step for the fabrication of the novel high speed pHEMT devices. The experiments focused on the elimination of “hump” structure as a result of an incomplete etching process at the InGaAs cap layer. In this work, two types of test samples were used, namely bulk InGaAs and epitaxial structure together with an etch stop layer. The result showed...
Linear modelling of novel InGaAs/InAlAs/InP pHEMT for low noise applications is substantial to the future transistors that will operate in high speed and low noise conditions. The novel pHEMT is constructed by sandwiching two different materials together with different lattice constants, for instance InGaAs and InAlAs in order to form a heterojunction in between. However, InP is only utilised to be...
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