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This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
Resistive switching memories have been identified as an enabling technology for a variety of emerging computing applications, including neuromorphic and logic-in-memory computing. For example, analog tuning of the memory state combined with high integration density of memristors is needed for very compact implementation of synapses, the most numerous devices in artificial neural networks and would...
In this work, we report about defects generation in the oxide layer of n-FinFETs during stress. Defects generation is probed using RTN traces collected at both the drain and the gate. A stress/measure approach is used to monitor the characteristics of the device, including RTN, at different levels of cumulative stress. Indicators derived from IG-VG and ID-VG measurements suggest defects generation...
We demonstrate the effectiveness and limitations of critical performance elements in silicon channel bulk finFET CMOS devices featuring embedded Source/Drain (e_SD) dual epi. Further scaling of the fin width below 10nm is shown to impact both the access resistance and S/D overlap capacitances while the mobility behavior for both nMOS and pMOS devices further degrades. Epitaxial S/D regrowth options...
A detailed statistical characterization of drain current local and global variability in sub 15nm gate length Si/SiGe Trigate NW pMOSFETs is carried out. An analytical mismatch model is used to extract the main matching parameters. Our results indicate that, despite their very aggressive dimensions, such devices maintain relatively good variability performance.
We assess the impact of the conductance response of Non-Volatile Memory (NVM) devices employed as the synaptic weight element for on-chip acceleration of the training of large-scale artificial neural networks (ANN). We briefly review our previous work towards achieving competitive performance (classification accuracies) for such ANN with both Phase-Change Memory (PCM) [1], [2] and non-filamentary...
AlGaN/GaN nanowire omega-FinFETs have been fabricated and characterized. Tetramethylammonium hydroxide (TMAH) lateral wet etching and atomic layer deposited (ALD) HfO2 sidewall spacer result in very sharp vertical edges and fin widths from 200 nm down to 30 nm. Omega-gate structure exhibits excellent gate controllability and separates the channel from the underlying thick GaN buffer layer, which leads...
In this paper, we investigate the impact of Ta and Ta2O5 thickness and of thermal treatment for the Ta2O5 layer on the forming and switching characteristics of Pt/Ta2O5/Ta/Pt ReRAM devices. The forming voltage (VFORM) decreases with increasing Ta and decreasing Ta2O5 thickness. However, VFORM saturates (∼ 2 V) for thicker Ta layers. Thinner Ta2O5 switching layer can further reduce the forming voltage...
The contact resistance RC of “edge-contacted” metal-graphene interfaces is systematically studied. Our experiments demonstrate a reduction of contact resistance by intentional patterning of graphene to create “edge contacts”. The parameter space for different hole patterns in graphene is explored. The contact resistance is reduced from 1518 Ωµm for structures without holes to 456 Ωµm in structures...
We report on the layout effects in strained SiGe channel FDSOI pMOSFETS down to 20nm gate length. Two SiGe integration schemes are compared: the SiGe-first approach, with Ge-enrichment performed prior to the STI module and the SiGe-last approach using only a SiGe epitaxy after the STI module. We evidence reduced layout effects in the SiGe-last integration featuring Si/SiGe bilayer. SiGe-last shows...
Interest in resorbable and biodegradable materials originates from their potential in food packaging, environmental science and ecology, but also in medicine and biotechnology. Till very recently, electronics has not been on such development paths. However, recent advancements in material science, thin processing and nanotechnology offer the prospective of high performance electronic devices which...
The performance of the GaN-based tri-gate HEMT is investigated by 3D numerical simulations. The tri-gate concept is shown to provide normally-off operation and to effectively suppress short-channel effects (SCEs). Furthermore, it is shown from our simulations that tri-gate AlGaN/GaN HEMTs can exhibit higher breakdown voltages and operate closer to the theoretical limit for GaN devices than their planar...
3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives...
In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with Ion of a couple of µA/µm (|VGS| = |VDS| = 0.5V) combined with average subthreshold...
The discovery of ferroelectricity in HfO2 and ZrO2 based dielectrics enabled the introduction of these materials in highly scalable non-volatile memory devices. Typical memory cells are using a capacitor or a transistor as the storage device. These scaled devices are sensitive to the local structure of the storage material, here the granularity of the dielectric doped HfO2 layer, varying the local...
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