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This paper will examine challenges in future device scaling and the implications arising from difficulties in delivering scaling benefits from devices to the circuit level, and ultimately up to the system level. These implications will serve to highlight opportunities in design-technology interactions to aid in overall system scaling.
SCM application gives ReRAM opportunity to become mainstream technology, beyond embedded field. Memory reliability improvement and memory/selector co-optimization are still required. To offer better performance/cost trade-off and differentiate from other technologies are necessary for ReRAM to step forward.
Nonvolatile power-gating (NVPG) that is a power-gating architecture employing nonvolatile retention is expected as a highly efficient energy reduction technique for high-performance microprocessors and mobile/wearable SoC devices. In this paper, the NVPG architecture for SRAM is demonstrated. A 1kb nonvolatile SRAM (NV-SRAM) array with the peripheral circuits is implemented using 65nm silicon-on-thin-buried-oxide...
While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ...
Building reliable mixed-signal circuits in advanced process technologies requires an accurate understanding of device performance and variability. This work presents an on-chip transistor characterization platform built on a digital focal plane array readout circuit framework that enables highly parallel device measurements to be taken in the digital domain. This technique is used to quickly assess...
This paper presents for the first time a TFET/CMOS hybrid CAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications like the IoT (Internet of Things). Proposed design is low power, area efficient and re-configurable i.e. can either be used as CAM or normal SRAM or as a combination of both. The simulation extractions for power and speed are done including wiring and...
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