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This paper presents an area efficient architecturefor quadruple precision division arithmetic on the FPGAplatform. Many application demands for the higher precisioncomputation (like quadruple precision) than the single anddouble precision. Division is an important arithmetic, butrequires a huge amount of hardware resources with increasingprecision, for a complete hardware implementation. So, thispaper...
Register files (RFs) consume significant power in low-power processors, and their specifications vary substantially for different applications. Challenges exist in identifying the appropriate RF design and optimizing RFs for different specifications. This paper not only explores methodologies of designing low power and high performance RFs and it also extends a virtual prototyping (ViPro) tool to...
Physical Unclonable Functions (PUFs) use random physical variations to map input challenges to output responses in a way that is unique to each chip. PUFs are promising low cost security primitives but unreliability of outputs limits the practical applications of PUFs. This work addresses two causes of unreliability: environmental noise and device aging. To improve reliability, we constructively apply...
The recently proposed three-dimensional (3D) integration promises to enhance the system performance. However, it poses several test challenges. Thermal safety of the 3D system is the foremost concern. Testing of the system plays an important role to improve the yield. This work presents a thermal-aware core test scheduling technique in 3D stacked multicore system using Particle Swarm Optimization...
In this paper, a novel voice based User-Device (UD-) physical unclonable function (PUF) is demonstrated. In traditional PUFs, variability of challenge-response pairs (CRPs) only comes from physical randomness of silicon. Recently, a new type of PUF, touch screen based UD-PUF is proposed, which entangles human user biometric variability with the silicon biometric. Any silicon based mobile device sensor...
With current tools and technology, someone who has physical access to a chip can extract the detailed layout of the integrated circuit (IC). By using advanced visual imaging techniques, reverse engineering can reveal details that are meant to be kept secret, such as a secure protocol or novel implementation that offers a competitive advantage. A promising solution to defend against reverse engineering...
Since the past decade Network-on-Chip has evolved as the most dominant and efficient solution in on-chip communication paradigm for multi-core systems. With the growing number of on-chip processing cores modern three dimensional NoC design is facing several challenges originating from various network performance parameters like latency, hop count etc. Scalability and network efficiency have generated...
Continuous technology scaling and increased demand for computational power have introduced a paradigm shift in manycore design requirements. On the other hand, tight power budgets and limitations of voltage scaling are throttling the ability to optimally exploit the potential of these systems, leading researchers to adopt aggressive voltage scaling techniques such as Near-Threshold Computing (NTC)...
Body biasing (BB) in bulk CMOS is an important tool for circuit designers that enables dynamic modulation of device thresholds post-fabrication, thus potentially improving yields, or allowing the circuit to adapt to different power modes, such as fully active or sleep. Fully-depleted silicon-on-insulator (FDSOI) FETs, such as ultrathin body (UTB) devices, may benefit from the same effect when the...
Spin-transfer torque random access memory (STT-RAM) has emerged as a promising nonvolatile memory technology for its fast speed, small footprint and zero standby power. However, the unique and unusual high asymmetric error rates at different memory bit operations, which are proved to be far beyond the efficiency of common error correction codes (ECCs), greatly hinder its applications. In this work,...
Energy consumption has become a major concern in portable applications. This paper proposes an energy-efficient design of the Secure Better Portable Graphics Compression (SBPG) Architecture. The architecture proposed in this paper is suitable for imaging in the Internet of Things (IoT) as the main concentration is on the energy efficiency. The novel contributions of this paper are divided into two...
Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks...
The paper describes a method of verifying sequential arithmetic circuits by adding a special type of redundancy, called "Vanishing Polynomials" and "Don't Care Polynomials". The proof of functional correctness consists in transforming the polynomial expression at the primary outputs into a unique polynomial in the primary inputs and comparing the computed...
This paper presents a post-placement technique for through-silicon-via (TSV) induced thermal mechanical stress reduction. Thermal mechanical stress causes several critical failures such as material fracture (interfacial delamination and silicon substrate cracking) and TSV stress migration (SM). The von Mises stress is used as a material fracture metric. An analytical TSV SM model is used, which replaces...
Physically Unclonable Functions (PUFs) were introduced over a decade ago for a variety of security applications. Silicon PUFs exploit uncontrollable random variations from manufacturing to generate unique and random signatures/responses. Existing research on PUFs has focused on either PUF design at the architectural level or optimization of lithography to increase sensitivity to random process variations...
The globalization of Integrated Circuits (ICs) supply chain has raised security concerns on how to ensure the integrity and the trustworthiness of fabricated circuits. While existing attack and protection methods are developed for CMOS based circuits, the introduction of emerging transistors acts as a double-sided sword. The usage of emerging devices introduces new security issues which the attackers...
A variety of hardware security primitives have been developed in recent years, aimed at mitigating issues such as integrated circuit (IC) piracy, counterfeiting, and side-channel analysis. For example, a popular security primitive for mitigating such hardware security vulnerabilities is the physical unclonable function (PUF) which provides hardware specific unique identification based on intrinsic...
In modern smart building climate control systems, accurate detection of unusual behavior in temperature sensors (outliers) can help reduce or prevent waste of energy consumption in a Heating, Ventilation and Air Conditioning (HVAC) system. In this work, we propose online learning-distance based outlier detection method. In the new method, we train and tune a multilayer neural network to learn a nonlinear...
Cyclostationary feature detection for spectrum sensing incognitive radio network has significant prospect in future wirelesscommunicationsystems. This work deals with the very-large scaleintegration(VLSI) architectural transformation of such detection algorithmfor field-programmable gate-array (FPGA) prototyping andapplication-specific integrated-circuit (ASIC) design. System level designof this detection...
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