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Physically Unclonable Functions (PUFs) were introduced over a decade ago for a variety of security applications. Silicon PUFs exploit uncontrollable random variations from manufacturing to generate unique and random signatures/responses. Existing research on PUFs has focused on either PUF design at the architectural level or optimization of lithography to increase sensitivity to random process variations...
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available. 1 KB SRAM is used as test setup for which on-chip read access time measurement is performed. On-chip delay measurement is performed using...
This paper presents a method to use floating gate (flash) transistors to implement low power ternary-valued digital circuits targeting handheld and IoT devices. Since the threshold voltage of flash devices can be modified at a fine granularity during programming, our approach has several advantages. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed...
Power gating (PG) is an effective power efficiency improvement technique. Future general-purpose graphics processing units (GPGPUs) will likely feature hundreds of compute units (CUs) and be power constrained, which leads to serious challenges to existing PG methodologies. In this paper, we propose novel design-time and run-time techniques to effectively implement power gating in future GPGPUs. Based...
We present an integrated hardware/software architectureto enforce security in networked workstations andembedded devices such as printers and microscopes. Thesedevices are usually connected to the Internet without protection, so they are exposed to attack. Our solution operatesas an intermediate isolation and protection module (IPM) between the network and the device to be protected. TheIPM can be...
In this work, an InSb/Si heterojunction hetero gatedielectric double gate TFET (HTFET) having a split pocket atSource-Channel junction has been designed and its analog/RFperformance has been investigated. The analog/RF performanceof the device is analysed in terms of I-V characteristics, transcon-suctance (gm), parasitic capacitances, cut-off frequency (fT) andgain bandwidth product (GBW). Maximum...
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