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As the device size decreases, the reliability degradation caused by soft-errors and multiple component error due to a single soft-error are becoming serious problems in VLSIs. In this study, we propose a method to synthesize single soft-error tolerant datapaths based on soft-error detection by duplication and comparison and correction by retry. Under the assumption that a single soft-error does not...
Reliability is a significant strategy concern for modern day multi core embedded systems. On chip communicating systems are vulnerable to permanent network faults and transient faults which might essentially affect the performance of the system. Targeting at fault tolerance solution for cores with faults in Network on Chip (NoC), this paper proposes an energy efficient fault tolerant NoC architecture...
Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
State-of-the-art techniques for enhancing system-levelreliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability evaluation of the network topology. In this paper, we apply the...
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