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A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS...
A non-volatile programmable logic (NPL) with atom switch significantly accelerates performance of micro-controller unit. A low-power 32bit-CPU using a 65 nm-node Silicon-on-Thin-Box (SOTB) CMOS performs 1.95 DMIPS/MHz and 33 µW/MHz on 25 MHz and VDD=0.4V. When a software process in the CPU is offloaded to NPL, the 9 times faster processing speed and 3 times higher energy efficiency are realized. A...
This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by...
The tunneling FET (TFET) is a leading option for energy efficient computation with peak logic performance/watt greater than CMOS. With variation effects, TFET reaches 2X higher peak efficiency than MOSFET by using supply voltages under 0.4V. Dense TFET SRAM bitcell is proposed with VMIN matching this low logic VDD. Projections of device variation enable a comparison of TFET and MOSFET logic and memory...
Critical switching current, Isw, of STT (Spin Transfer Torque)-MRAM has been reduced by several orders with perpendicular MTJ and the state-of-the-art write charge, Qw, becomes the order of 100–150fC. With the small Qw, MRAM starts to save energy consumption by 70–80% compared with a conventional memory system. Analysis of the write pulse-width dependence of Iw revealed a further potential of perpendicular...
In the years between now and 2022, the foundation for automated driving will be developed. Automated driving will not be introduced in the market at once and not with the same electrical and electronics (E/E) architecture; it will be introduced piece by piece and in different forms of E/E architectures. The main reasons for automated driving will always be the same: comfortable, efficient and safe...
In this work, we report a one-transistor (1T) versatile memory; the memory transistor characteristics achieve sub-60-mV/dec operation and considerably low off-state leakage of 10−15 A/µm at a supply voltage below 0.5V. The versatile memory features DRAM/NVM functions of large ΔVT window of 2.8V, fast 20-ns speed, 103s retention at 85°C, and long extrapolated 1016 endurance at 85°C, which show the...
We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/µm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide...
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
This paper addresses automotive low power technologies in Internet of Things (IoT) societies, where the interaction among cloud information, real-time recognition and vehicle control is a key. High reliability and high performance with low power under the harsh operating conditions are strongly demanded for automotive microcontroller units (MCUs). Our developed embedded Flash (eFlash) and SRAM achieved...
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