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A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS...
For the first time, we present a Phase Change Memory (PCM) device with an optimized Ge-rich GeSbTe (GST) alloy integrated on a 12Mb test vehicle. We confirm that PCM can guarantee high data retention in extended temperature range and we provide the understanding of the high thermal stability of the two programmed states. We show how the elemental distribution reaches an equilibrium at the core of...
A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1−x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.
We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (Rwire) multiplied by logic gate input pin cap (Cpin), Rwire×Cpin, is identified as a major limiter of performance and power at N7. Reducing Cpin is crucial to...
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction...
We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity...
A low-power 2Mb ReRAM macro was developed in 90 nm CMOS platform, demonstrating lower power data-writing (x1/7) and faster data-reading (x2∼3) as compared to a conventional flash. The memory window at −6σ for 10 years was confirmed with a high-speed 1-bit ECC considering operating temperature ranging from −40 to 85 °C, where the worst conditions are high-temperature (85°C) “Off” writing and low-temperature...
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