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A high spatiotemporal resolution, wireline operation-based, in-vivo neural recording system is presented. The proposed system allows selecting 64 channels from 512 recording sites. The neural signals from the 64 selected sites are amplified, filtered, and finally multiplexed in the time domain. The output signals of each multiplexer are buffered, converted to the current domain, and then transferred...
In this paper a comparison of four low noise amplifiers (LNAs), designed in fully depleted SOI 28 nm technology, has been presented. The objective of the presented work was to verify the usability of all kinds of MOSFET transistors that are available in UTBB for RF analog designs. The inductively degenerated cascodes were used in simulations. Such topology achieves high gain and low noise figure (NF)...
The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The...
Two simple non-iterative methods of MOSFET threshold voltage parameter extraction are presented. They are valid for threshold voltage-based and charge-based compact models of MOS transistors. The methods take advantage of the features of the model formulae and their derivatives. The methods have been illustrated using both real measurements and data obtained via simulation of simple circuits used...
Among the numerous solutions developed to improve the handling capability of superjunction power devices, the Deep Trench Termination (DT2) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of...
Thermal characterization techniques require precise powering and accurate data acquisition equipment. The proper powering is complex due to electrical and thermal stability issues and some device properties. A few methods require trials to ensure the proper powering of the devices. New compound semiconductor devices have further stability issues at low currents and high voltages. This paper analyzes...
In CMOS electronics using differential pairs, input signals are usually supplied to gate terminals of MOS transistors creating the pair. Then, the tail terminal of the pair is used to ensure the required bias needed for proper operation of the transistors. In this paper, we show that roles of the gate and tail terminals can be changed. This implies, among others, that the tail can be used as a terminal...
New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example,...
This paper presents a semi-empirical model of the mobile charge in the channel of a junctionless dual-gate MOSFET. Its accuracy has been demonstrated to be better than 1% of the total depletion charge for a wide range of channel thickness and substrate doping values.
This paper devotes to a new 7-2 compressor designed according to a new architecture with a pure Glitchless output. A considerable increase in the speed of the operation is achieved by utilizing a new truth table, fast production of signals Cout1 and Cout2, optimum tuning of the width of the utilizing transistors, and eliminating the parasitic capacitances through merging the drain of transistors....
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