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Customer demands for battery powered portable electronic devices have increased. Today high data rates could be transmitted using fourth generation Long-Term Evolution (4G LTE) wireless communications standard. To increase system runtime proper envelope amplifier's architecture has to be selected. Using envelope tracking technique efficiency of the transmitter's power amplifier (PA) can be improved...
In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is...
In this paper we present a novel successive approximation register (SAR) analog-to-digital converter (ADC) designed for the applications that demand many such converters working in parallel in a single chip. For this reason we have put a special emphasis on a very low chip area and low power dissipation. The ADC operates in the current-mode. The digital-to-analog converter (DAC), which is one of the...
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