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This paper presents a low-power optimization technique (LPOT) for a 1V pipelined RISC microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPOT, a 32-bit pipelined RISC microprocessor test circuit having 144,000 transistors with 3 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells...
Embedded software is at the heart of many systems, including critical ones. It is therefore often mandatory to precisely identify, for a given application, the robustness level achieved with respect to various perturbations. This paper is focused on soft errors occurring in internal registers of pipelined processors. Two criticality evaluation approaches are compared; one based on criteria evaluated...
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