The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The multicore processors are becoming norm and a processor with even more than a hundred of cores are emerging. These inherently require wide range of software tools to help software developers. However, supporting these complex hardware by the tools require significant effort by the tool vendors, and each invest in adapting the new hardware by modifying their tools or creating proprietary configuration...
On behalf of the advisory committee of COOL Chips XVII, I extend greetings to each of the conference attendees. The productive goal of this conference is to be part of the premier/leading conference series on microprocessor architecture and technology. This rapidly growing field still regularly and aggressively produces innovative ideas and corresponding products for the cyber world around us day...
Welcome to COOL Chips XVII, an international symposium that provides you with the latest developments on low-power and high-speed chips. This year we are bringing you an exciting program that includes five keynote speeches, three instructive special sessions and one panel discussion in this noble harbor city of Yokohama.
It is my pleasure to welcome you to the COOL Chips XVII, the 17th IEEE Symposium on Low-Power and High-Speed Chips. COOL Chips Conference Series started in 1998, which was held in Tokyo as a one-day event of invited talks only. Now COOL Chips is a three-day event fully sponsored by IEEE Computer Society, which covers not only the chip architecture design, but also software technologies at system software...
A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14µA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.
Data races in parallel programs are notoriously difficult to detect and resolve. Existing research has mostly focused on data race detection at the user level and significant progress has been made in this regard. It is difficult to apply detection methods designed for user-level applications to identify OS kernel level races. In this paper, we present a new detection tool that is able to effectively...
We propose a low power refresh control scheme for 3D stacked DRAM memory, which leverages the data-pattern dependence characteristics of the cells' Retention-Time to squeeze the margin of refresh interval. It is a systematic approach that uses our proposed Retention-Time (RT) detection mechanism to capture the bottleneck that contributes to over-frequent refresh operations: “weak” cells with relatively...
Recently, dual or triple modular redundancy (DMR/TMR) has been commonly used in high-end server or special environment targeted microprocessors to mitigate single event effects (SEEs), as the miniaturized transistors tend to be more vulnerable to SEEs. However, facing the issue that DMR and TMR usually add remarkable pressures to the power consumption due to the highly redundant executions, this work...
Now we are enjoying the mobile computing era mainly with smart phones. This is a fruit of the continuous downsizing of computing devices, and further downsizing will realize a wearable computing era. Some wearable devices have been already available or announced today, and the shift to the new era is ongoing. We can enjoy a network infrastructure in many situations, although its speed, response time,...
Since idle-state is the dominant state for embedded systems, disabling unused devices in idle-states can lead to significant power reduction. Among the various sleep modes provided by application processors, Deep Sleep mode offers maximum power savings. Since Deep Sleep mode requires to stop I/O devices and clocks, it is usually used in suspend-state. However, with the emergence of non-volatile or...
Replacing of DRAM in main memory with non-volatile memory (NVM) has several merits. However, NVM under development has some limitations in write operation. To overcome it, some previous researches proposed NVM/DRAM hybrid memory architecture. In the architecture, it needs to determine data placements between NVM and DRAM. In this paper, we advocate that programming language runtimes are useful for...
In this work, we propose the Explicit Redundancy Linear Array (EReLA) architecture to provide a highly flexible fault-toleration, which effectively utilizes its rich resources in a functional unit (FU) array for both the error detection and the fail-safe hot-swap after taking a permanent fault. For the preparation of the hot-swap, a self-tuning scheme is proposed specifically to fast locate the precise...
This paper presents a parallelization method utilizing dead time to implement higher precision control systems on multi-core processors. It is known that dead time is hard to handle with in control systems. In our method, the dead time is explicitly represented as delay blocks of models such as Simulink. Then, these delay blocks are distributed to the overall systems with equivalent transformation,...
A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.