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We demonstrate a monocrystalline 1×8 μm germanium gate photoMOSFET integrated with silicon photonic waveguides and grating coupler operating at over 2.5 GB/s at 1550nm.
The information age has produced astonishing improvements in compute power, but the current highly successful CMOS technology is running into power limitations. Computing takes up of order 5% of the US electricity production, power is now the primary limiting factor on clock speed, and power limits practical development of exascale computing facilities. CMOS power depends on voltage which is now limited...
The active search for candidates of an ideal switching device for low-voltage logic and ultralow-power applications has stimulated focused explorations of contact-mode switches (relays) based on micro/nanoelectromechanical systems (MEMS/NEMS) [1-7]. This has been driven by the fundamental advantages that mechanical devices offer, such as ideally abrupt switching with zero off-state leakage, suitable...
We present on an optical antenna based nanoLED that is fabricated directly on top of an InP waveguide. Waveguide coupling efficiency of 70% and directional emission is achieved with a Yagi-Uda antenna structure. By using an epitaxial lift-off process, we show that this device could be integrated directly onto a Silicon-photonics substrate.
Within the past decade, the semiconductor computing industry has developed multicore and multithreaded core processors to overcome the challenges and shrinking benefits of traditional technology scaling. Multichip systems built using these components will require immense amount of off-chip bandwidth and low latency chip-to-chip links at the lowest energy cost possible. Wavelength-division multiplexed...
Nanoelectronics based on 2-dimensional layered materials is a field of rapidly growing interest. In particular, graphene and transition metal dichalcogenides (TMD) exhibit remarkable properties that can be exploited for many applications. Most electronic devices based on 2D materials, however, focus on the electronic properties of the material: 2D materials are usually utilized as semiconducting pathways...
From mobile devices to data centres, energy usage in computing continues to rise and is now a significant part of global energy consumption. Increasing the energy efficiency of computation is a major concern in electronic system engineering and high on the research agenda worldwide. While hardware can be designed to save a modest amount of energy, the potential for savings are far greater at the higher...
The rise of dark silicon is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. In this talk I examine two new frameworks employed by computer architects to understand the challenges and opportunities that await us. The first is the utilization wall [2], a simple model that architects use to understand how technology scaling under post-Dennard assumptions...
Emerging spin transfer torque (ST) devices such as lateral spin valves and domain wall magnets may lead to ultra-low-voltage, current-mode, spin-torque switches that can offer attractive computing capabilities, beyond digital switches. This paper reviews our work on ST-based non-Boolean data-processing applications, like neural-networks, which involve analog processing. Integration of such spin-torque...
Moore's law, the driving force behind the semiconductor for the past decades, is endangered from several angles. Artifacts of scaled dimensions, yield, reliability, fabrication cost and device performance degradation all raise legitimate concerns about current trends of mere transferring same architectures to more advanced substrates.
High performance servers of data centers for cloud computing consume immense amounts of energy even though they are usually underutilized because they provide huge computing capabilities. In times when not all of those computing capabilities are needed the task to be solved is how to distribute the load in a power-efficient manner. The research question is: How should a requested compute load be mapped...
To date, TFET results have been unsatisfying. The best reported subthreshold swings have been measured at a current density of around a nA/um and get significantly worse as the current increases. In order to achieve a better performance, there are fundamental design issues that need to be engineered. We can understand these issues by analyzing the three types of devices shown in Fig 1. The voltage...
This work presents the effect of servers and racks heat capacity on common dynamic scenarios in data centers. Room level Computational Fluid Dynamics (CFD) model is developed to simulate airflow rate and servers power fluctuations in a representative data center. It is found that the servers heat capacity has a significant effect on the dynamics of data centers. An order of magnitude increase is observed...
The current MPI+Fortran ecosystem has sustained HPC application software development for the past decade, but was architected for coarse-grained concurrency largely dominated by bulk-synchronous algorithms. The trends in computer architecture have turned our model for how to get good performance from computing systems upside-down, and will require rethinking our entire programming environment and...
Monitoring the dynamic power utilization of enterprise computer servers in large-scale data centers is a non-trivial undertaking. Real-time power monitoring is essential for power management and intelligent cooling provisioning and is motivated by the fact that the energy costs for many classes of servers now exceeds the initial hardware costs for the servers. The conventional approach for dynamic...
Compute performance increased by orders of magnitude in the last few decades, made possible by continued technology scaling, increasing frequency, providing integration capacity to realize novel architectures, and reducing energy to keep power dissipation within limit. The technology treadmill will continue, and one would expect to reach Exascale level performance this decade; however, it's the same...
2-dimensional (2D) electronic materials such as graphene have emerged as attractive candidates for tunnel devices and circuits for achieving ultra-high energy-efficiency. This paper highlights a few novel tunnel device and circuit concepts based on graphene. Major challenges of 2D materials relevant to such applications are discussed as well.
Significant physical challenges remain for CMOS technology to decrease Ioff as transistor dimension and power supply voltages continue downscaling. However, a fundamental thermodynamic limit in the subthreshold slope SS = |(∂Vg)/(∂lnId)| = ln10 · kBT/q at >60 mV/dec exists at room temperature. We have designed and demonstrated the first semiconductor nanowires (NWs) and nanoelectromechanical system...
Tunneling field-effect transistors (TFETs) have created excitement for their potential to overcome the 60 mV/decade thermal limit of the subthreshold swing for conventional devices enabling lower power electronics. However, as shown in the TFET review by Seabaugh and Zhang [1], experimental subthreshold characteristics have not achieved the steepness of theoretical predictions. Possible explanations...
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