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This paper deals with the monolithic integration of switching cells that are used in power electronics for the realization of static power converters. The aim of the monolithic integration of the power switching cells is to suppress wire bonding in order to improve electrical performance as well as reliability of power modules intended for medium power applications. Within this context, the single...
This paper presents design approaches focused on application of amplifiers structures in High-voltage technology processes with special regards to Silicon-on-Insulator ones. Voltage-mode and current-mode approaches are taken into account and implemented. The presented topologies are discussed and HV application potential of current-mode is pointed out.
This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values...
Methods of a MOSFET threshold voltage extraction have been briefly described. A possibility of their application for characterization of a fully-depleted SOI MOSFETs has been discussed. A simple method for SOI MOSFET threshold voltage characterization has been proposed. The concept has been verified based on experimental data obtained for SOI MOSFETs manufactured in ITE.
Continuous technology advancements have forced MOSFET architecture to evolve from bulk to SOI to multigate MOSFETs. BSIM compact models have helped circuit designers to realize their designs first time correct using accurate physical models used in SPICE simulation. BSIM3 and BSIM4 are threshold voltage based bulk MOSFET models while BSIM6 is charge based bulk MOSFET model, which include physical...
A 2D physics-based model for short-channel junctionless double gate (DG) MOSFETs is presented. From a closed-form solution for the 2D potential we derive explicit equations for the calculation of threshold voltage VT and subthreshold slope S. A unified charge model valid for all operating regimes is developed by using Lambert's W-function, and a standard smoothing function for the transition between...
In this work, we present the technological constrains and limitations in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters. This work could serve as a guideline for technology...
This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×1018 atoms/cm3. The devices demonstrate up to six decades of Ion/Ioff ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.
A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order...
This paper presents a new high speed, low power 5-2 compressor which is constructed according to a sensible combination of pass transistor logics and static logics. The 5-2 compressor is designed based on a new truth table that is obtained by performing some changes on its conventional truth table. So simple structures are obtained in which capacitances of middle stages are decreased. Therefore, a...
This paper presents ways of enable and power-down functionality implementation in HV SoI buffers. Several HV buffer topologies are taken into account. Power-down, high input and output impedance functionality implementation approaches are presented and discussed.
Delay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is breaking the link between dynamic power and data...
The paper describes structure and simulation results of the novel ring oscillator designed in UMC CMOS 0.18 µm (1.8 V). Frequency generated by the oscillator is tuned by scaling the supply voltage, additionally ring length is digitally controlled. Presented ring oscillator has very wide tuning range (250 MHz–2.1 GHz) with small current consumption (34–689 µA).
What decoder is, everyone knows. The paper presents a method of n-to-2n-lines decoders design in easy way. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library Moreover, some important parameters, such area, power dissipation...
Currently electro-thermal simulations performed with 3D FEM simulators like ANSYS or COMSOL Multiphysics are limited to an imposed current flow through resistive materials. However, in the case of power MOS gated transistors like VDMOS transistors or IGBT, the channel resistance evolves with the gate voltage. This phenomenon is usually neglected in ON-state applications but seems to be determinant...
In the last few years the Tunnel-FET has become one of the promising devices to be the successor of the MOSFET due to its CMOS compatibility and steep subthreshold slopes (S) below 60 mV over dec. In this paper a 2D physics-based analytical model for Tunnel-FETs is introduced. It predicts a 2D band-to-band tunneling probability calculation through Wentzel-Kramers-Brillouin approximation (WKB) based...
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