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This paper presents a simple circuit technique to reduce gain variability with temperature in cascode amplifiers using a body-biasing scheme, and at the same time, enhance the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that it is possible to obtain supply-and-temperature-compensation...
This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values...
The state-of-the-art scaled down CMOS processes have led to devices with extremely high Ft reaching several hundreds of GHz. This high Ft can be traded with power consumption by moving the operating point towards weak inversion with Ft reaching tens of GHz, high enough for many modern RF applications. The new charge-based bulk compact MOSFET model BSIM6 was developed with the objective to provide...
In this paper a new approach for technology migration of analogue CMOS circuits is presented. The Hooke-Jeeves algorithm and genetic algorithms, are considered for multi criteria optimization in conjunction with HSPICE simulation software. Their goal is to calculate the values for circuits' elements for implementation in certain technology of fabrication. The modifications and improvements introduced...
What decoder is, everyone knows. The paper presents a method of n-to-2n-lines decoders design in easy way. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library Moreover, some important parameters, such area, power dissipation...
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